Added new SRAM memory interface meant for connection to data refill port. First draft!
Also added a missing signal to the WB interface, the lane select.
Fixed line invalidation logic for writethrough in cache.
Added Simulation scripts for new "application module" TB.
Added new "application" module.
Meant as a demo application of the core, only a first draft.
Updated the cputest SW to test byte reads and writes to cached RAM.