build: new target "prog" which flashes the FPGA
       from command line.
vetar_sdc: fix timing violations of Butis_to_timestamp core
           cutting clocks domains
Merge branch 'asterisk' into proposed_master

Conflicts:
	top/gsi_vetar/wr_core_demo/vetar_top.sdc
scu: fix onewire base address -- real fix pending please!

The onewire base addess is hard-coded AND wrong.
Stefan is working on a proper fix.
wb_irq: distinguish master and slave wb_irq interfaces
wb-pcie: include driver bug fix
flash: use 4x lane spi on arria5 power-up
flash: update flash tool to cope with new controller
flash: include a tool to write the non-volatile config register