Add RegisterFile
Control Unit (without delays)
Adjus convention for outputs
Data Memory
Added ALU_control
input and output edited to vectors
Add ALU V2
Merge pull request #2 from fakhreldin-m-abdelkhalik/CU

Cu
Remove a useless file
Change memory size to 1024
change dependency to Address not clock
32 bit input MUX & 5 bit input MUX
Sign extension unit
Merge pull request #3 from fakhreldin-m-abdelkhalik/Amr_ALU

Add ALU V2
continous assignment for output data
Merge pull request #6 from fakhreldin-m-abdelkhalik/sign_extension

Sign extension unit
fix posedge clock
Adjust Errors at Reading
Merge pull request #4 from fakhreldin-m-abdelkhalik/data_memory

Data memory
Reg to wire and assign