net: asix: don't pad odd-length TX packets

For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that
they have an even size. Currently, asix_recv() does remove this padding,
and asic_send() adds equivalent padding in the TX path. However, the HW
does not appear to need this packing for TX packets in practical testing
with "ASIX Elec. Corp. AX88x72A 000001" Vendor: 0x0b95 Product 0x7720
Version 0.1. The Linux kernel does no such padding for the TX path.

Remove the padding from the TX path:

* For consistency with the Linux kernel.
* NVIDIA has a Tegra simulator which validates that the length of USB
  packets sent to an ASIX device matches the packet length value inside
  the packet data. Having U-Boot and the kernel do the same thing when
  creating the TX packets simplifies the simulator's validation.

Cc: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
[Marek tested on 0x2001:0x3c05 DUB-E100 D-Link Corporation]
[Marek tested on 0x0b95:0x7720 ZoWii Zoltan Tech]
Tested-by: Marek Vasut <marex@denx.de>
[Gerhard tested on 0x0b95:0x772b ASIX Elec. Corp. AX88772B 000001]
[Gerhard tested on 0x0b95:0x772b ASIX Elec. Corp. AX88772B 0E62D5]
Tested-by: Gerhard Sittig <gsi@denx.de>
LATER: ARM: tegra: add support for more clocks on Tegra114

FIXME: work on this later after Tegra124 support.
FIXME: re-write commit description now it's been split up...

Some Tegra114 peripherals can take up to 8 different clock sources
(parents), including 4 new ones that don't exist on previous chips
(PLLC2/C3/MEM2/SRC2). Expand clock/PLL code/tables to support these
additional bits/sources.

Changes were made to some common code. Testing on Tegra30 and Tegra20
showed no changes in periph clock sources/divisors.

Also, peripheral clock sources that no longer exist on Tegra114 were
removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs
that are gone or not needed in early init are no longer brought out of
reset/enabled (FUSE, IRAMA/B/C/D, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* Undid change to assert on divisor value; the fix was applied to the
  wrong assert. The assert which should have been fixed was within the
  removed unused code.
v2:
- Fixed an assert test for a divisor value (s/b >0, not >=0)
- Remove some unused code
Revert "LATER: ARM: tegra: add support for more clocks on Tegra114"

This reverts commit 6cf0329f447d51e1ad5909d46f79cfd4756a4c93.
LATER: ARM: tegra: dalmore: add PMIC init for various peripherals

FIXME: work on this later after Tegra124 support.

These power rails are currently needed for kernel boot. This will be move
to a PMIC-specific driver (or even better moved to the kernel) at a later
date.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Revert "LATER: ARM: tegra: dalmore: add PMIC init for various peripherals"

This reverts commit 2e5b746676e5360325456184750e979726b4a009.