Added mraa examples based on documentation files

Signed-off-by: Dan Yocom <dan.yocom@intel.com>
Thomas Ingleby confirmed via email that Gen 2 has a shared pwm period, not a per-pin pwm period (as in Gen 1). Since this instance of `Pwm` is inarguably pin-specifc (ie. pin 3), anyone that wasn't aware of the change to pwm period control might just assume it works the same way as Gen 1.