Add a comment that a write to read only register will not work in the
supplied test case.
Change the default bad checksum from 0 to 0xdead as that is a lot
easier to distinguish from the reset value allowing us to easier
follow it in simulation.
Add an awk script that generates different combinatins of register
names for the python test framework expected by supplied tests.
Hook the result up to the simulation targets in the Makefile to always
append these when regenerating the registers.
Add a test that unloading the kernel driver actually worked and do
notproceed if it failed.  Otherwise the system will end up in a
hurly-burly state after the bitfile was programmed and often needs
a reboot to recover as the formerly laded driver will have references
one cannot clear and forcing will cause an oops.
Add pktdata.v, which is not a verilog file and should be .txt
which has the offsets into our packets for ethernet and IPv4 header.

Commit the Verilog which passes all software tests in simulation.

X-TODO: there are some unused wires and registers to be cleaned up.
Add a script that will run all provided and some of ours (skipping
earlier, interim stages) tests in either simulation or hardware and
write the output to logfiles.   For simulation it will re-run the
packet and register checks manually and write each to dedicated
files for easier (scriptable) detection of FAILs.
Change the python we call; the -nf is not in our path and it is
unclear to me what it is.
Add the new version with all our mappings included to allow
provided test cases to work.  This file is re-generated all the
time yet in git.
Add a short C program that dumps our registers(rather raw currently)
but can be easily extended to ,e.g., also dump tables, clear registers.
Also exclude the (provided) simple forwarding test as it does not seem
to program any tables and thus is not suitable at this stage anymore.
Merge branch 'master' of ssh://127.1:2222/Users/bz/Documents/Cambridge/CL/P33/P33.github