[software/VDIF_test.py] fixed to accommodate bit code _July_29_1224.bof.gz

This version of the software sets the VDIF headers correctly, with
the currently debugged and developed version of the VDIF headers.

Hard-coded in this bitcode are:
W0: bits 31 and 30
W1: bits 31 and 30
W2: ALL
W3: bits 31 to 26
W4: bits 31 to 24
W5: none
W6: ALL
W7: ALL

For the future: could probably assign all of W4 and all of W5 each
their own software register, and make all decisions about bit
meaning and allocation in software.  Currently it is broken up
into software registers and sliced in the FPGA to match the
ALMA EDV standard.