For BERI on NetFPGA assume HZ=100 by default.

Remove the uart support in favour of a "jtag-uart" interface imitation
providing a much simpler interface, directly exported to the host,
allowing the toolchain to be shared with BERI on Altera. [1]

Submitted by:	Jong Hun HAN (jong.han cl.cam.ac.uk) [1]
MFC after:	2 weeks