Support thumb code.  Add convience macros.
Move curpcb, curlwp, astpending, want_resched, current_spl_level,
and current_intr_depth to cpu_info.
Add support for storing either curlwp or curcpu in the ARMv6
supervisor process/thread id coprocessor register.
Add LWP0_CPU_INFO to store location of static cpu_info for lwp0 static
initialization.
Use cpsi[ed] on ARMv6.
On ARMv6, expand bswap32/bswap16 to a "rev" or "rev16" instructions.
Add space in pcb32 for the armv6 coprocessor registers which store the two
user thread/process ids (one is read-only, one is read-write by user).
Add thumb versions (or force to arm32 mode when in thumb mode).
More thumb support
Add thumb versions of crt0.
Add thumb support for syscalls > 255.  If embedded syscall # is 0, take
syscall number from ip register.
CPU functions for ARM Architecture V6.
Deal with astpending/want_resched move to cpu_info
Add curlwp_set() to set curlwp.  (This is for that architectures which have
a special CPU register which could be used to store curlwp (armv6, ppc)).
Pre-init the static structures (lwp0,proc0,session0,etc.) whenever possible.
Use curlwp_set()
Add ArmV6 pte/pde extensions.
Rototill to deal with curpcb/astpending/etc moves to cpu_info.
Make ENABLE_ALIGNMENTS_FAULT leave cpu_info in r4.
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS takes advantage of r4 being cpu_info.
Teach this about the new world order (cpu_info = r4, intr_depth in cpu_info)
#include "assym.h" first!
Deal with want_resched move to cpu_info
Update to new reality.
Deal with new world order.
Add ARM1176JS id.  Add ARM11 PMC definition.  Add cache P bit.  Add cpuconf
armv6 XP and UNAL enable bits.