gensdrphy: fix dm generation
make.py: init bios memory in build-bitstream action otherwise it is not possible to run clean or build-csr-csv or build-headers without build-bios
Use SDRAM on the Papilio Pro

Based on code by Robert Jordens
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
crt: add umoddi3
programmer: make xc3sprog verbose
spiflash: redundant slice
bios/crt0.S: remove unused macaddr, add syscall handler stub
crt0: remove macadress for or1k as well
targets/simple: pass kwargs
minimac: rewrite it with Migen, add HW acceleration for Ethernet preamble & CRC
changes:
- remove verilog code
- use dataflow from/to phy to/from the SRAM memories
- CDC from/to eth_rx/eth_tx is done directly on the dataflow, registers are in system clock domain.
- preamble can now be inserted/checked directly in hardware (enabled by default, but still support old software preamble generation)
- CRC can now be inserted/checked directly in hardware (enabled by default, but still support old software CRC generation)

errors behaviours:
- HW preamble check error: packet is not transmitted to the next dataflow module.
- HW CRC check error: packet is transmitted to the next dataflow module (since CRC is at the end of the frame), but is discarded
with the "discard" flag. SRAMWriter module will not generate an IRQ and will reuse the current slot for the next packet.

tests:
- netboot (10Ko binary): OK
- udp bandwith tx test: ~20Mbps with SW generated preamble&CRC, >50Mbps with HW generated preamble&CRC