hdl/modules/fmc_adc_common/*: fix 7SERIES idelay primitives

For 7SERIES FPGAs, the iodelay primitive has beed updated to
idelaye2. So, we add a differente generate for these FPGAs
hdl/modules/*: add g_delay_type on FMC ADC modules

Exposed the idelay type desired to user. This brings flexibility
on selecting the different delay types for different FPGA devices
hdl/*/*/fmc_adc_buf.vhd: fix wrong IOSTANDARD

For single-ended inputs, it is necessary to use
A single-ended standard, obviously