Initialize X86 DataLayout based on the Triple only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215279 91177308-0d34-0410-b5e6-96231b3b80d8
Remove extraneous 64-bit argument to the PPC TargetMachine constructor
and update initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215280 91177308-0d34-0410-b5e6-96231b3b80d8
Initialize PPC DataLayout based on the Triple only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215281 91177308-0d34-0410-b5e6-96231b3b80d8
Use the full form of dccci and iccci from the early PPC 405 documents,
since the operands are actually used on those cores. Provide aliases for
the only documented case in the newer Power ISA speec.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215282 91177308-0d34-0410-b5e6-96231b3b80d8
Update disassembler test to check the full dccci/iccci form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215283 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215284 91177308-0d34-0410-b5e6-96231b3b80d8
Allow the third argument for the subi family to be an expression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215286 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGen: switch to a range based for loop

Use a range based for loop instead of manual iteration.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215287 91177308-0d34-0410-b5e6-96231b3b80d8
MC: cleanup includes

Cleanup Win64EH header inclusion.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215288 91177308-0d34-0410-b5e6-96231b3b80d8
MC: remove duplicated code

This removes the duplicate definition of GetXDataSection.  This function is
available as a static method and is identical to the previous implementation.
This just cleans up the unnecessary duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215289 91177308-0d34-0410-b5e6-96231b3b80d8
Resolving some type truncation warnings in MSVC (enum to bool in this case). No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215293 91177308-0d34-0410-b5e6-96231b3b80d8
fixed typos


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215299 91177308-0d34-0410-b5e6-96231b3b80d8
ADT: remove MinGW32 and Cygwin OSType enum

Remove the MinGW32 and Cygwin types from the OSType enumeration.  These values
are represented via environments of Windows.  It is a source of confusion and
needlessly clutters the code.  The cost of doing this is that we must sink the
check for them into the normalization code path along with the spelling.

Addresses PR20592.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215303 91177308-0d34-0410-b5e6-96231b3b80d8
If available, pass down the Fixup object to EvaluateAsRelocatable.
At least on PowerPC, the interpretation of certain modifiers depends on
the context they appear in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215310 91177308-0d34-0410-b5e6-96231b3b80d8
Fix tabs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215311 91177308-0d34-0410-b5e6-96231b3b80d8
@l and friends adjust their value depending the context used in.
For ori, they are unsigned, for addi, signed. Create a new target
expression type to handle this and evaluate Fixups accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215315 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: correct isPredicable for MULS in ThHUMB mode

The ARM ARM states that CPSR may not be updated by a MUL in thumb mode.  Due to
an ordering of Thumb 2 Size Reduction and If Conversion, we would end up
generating a THUMB MULS inside an IT block.

The If Conversion pass uses the TTI isPredicable method to ensure that it can
transform a Basic Block.  However, because we only check for IT handling on
Thumb2 functions, we may miss some cases.  Even then, it only validates that the
CPSR is not *live* rather than it is not accessed.  This corrects the handling
for that particular case since the same restriction does not hold on the vast
majority of the instructions.

This does prevent the IfConversion optimization from kicking in in certain
cases, but generating correct code is more valuable.  Addresses PR20555.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215328 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for scalarizing cttz_zero_undef

Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.

Differential Revision: http://reviews.llvm.org/D4813


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215330 91177308-0d34-0410-b5e6-96231b3b80d8
Increase the size of PMTopLevelManager::ImmutablePasses from 8 to 16.

During a bootstrap build of Clang, this SmallVector always held 14 elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215333 91177308-0d34-0410-b5e6-96231b3b80d8
Increase the size of DwarfAccelTable::TableHeaderData::Atoms.

During a Clang bootstrap, it seems this SmallVector always contains 3 elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215334 91177308-0d34-0410-b5e6-96231b3b80d8