hdl: Making some timestamp changes.
hdl: Adding TX NOW and RX metadata gating.

Adding a zero sample to the beginning of the burst tests so initial
power out from the LMS is minimized.

I tried adding a single sample to the DAC output but it didn't seem
to want to work appropriately, so there is around 700us worth of output
power after an initial boot of the board and loading of the FPGA.
hdl: Sending a few more samples when first enabled

Helps mitigate the high default output power from the LMS after
initialization of the device.  The observed time appears <200us.