Add one callback function for hw_codec_info to initialize hw_codec_info

V1->V2: Refine the call back function name from hw_codec_hook to preinit_hw_codec
And it is called after VADriverContext is fully initialized. This is based on the comment
from Gwenole Beauchesne.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 33e62fda870dc5c9b482fb6a23260da9ae465806)
change the attribute of hw_codec_info so that it can be updated dynamically

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 065db8289d3f38a923959f87d1b75767a0633e61)
Encoding: Add one hook callback function to detect encoding capabilitiy on Haswell

Some Haswell machine doesn't support the encoding. So it should be disabled.
Otherwise the driver can't report the supported capability correctly.

V1->V2: Minor update based on comment from Gwenole Beauchesne. For example:
use the bool tye and remove the hardcoded value

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 23ae0f76ee5b3c097e6ae34182219cf44b09b82e)
Use the strncasecmp instead of strcasecmp to make it more robust

At the same time the extra string arrary is removed.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 05ece0c3698f4f48c4141e8bd0608b9869d8ad0c)
Check the value returned by strstr to avoid NULL pointer

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 021149c50ffd5c55d45acbda6bb950c7206b7255)
Use the inline CPUID assembly to obtain CPUID string instead of /proc/cpuinfo

On some systems there is no access to /proc/cpuinfo. So the inline assembly
is used directly to detect the CPUID string.

V2->V3: Follow the suggestion from Google engineer to remove the unused code
of "if 0". And the "unsigned int" data type is updated to "uint32_t".

V1->V2: Based on the Matt Turner's suggestion the __cpuid defined in GCC
cpuid.h is called directly, which is helpful to handle the PIC issue on
32-bit.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 3e8cce4e7292651af10c9f375a6ad2e9fa494021)
CHV: Add PCIID placeholders for CHV

Pending branding and differentiation by stepping.  CHV is used generically
to match libdrm and mesa identification.

Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
(cherry picked from commit 1121cb1f87228005a2b15b5ead95701a7fbe7519)

Conflicts:
	src/i965_device_info.c
1.4.1.pre1 for development

Sync news from V1.4-branch:
c8a8a406cffdccf046a2c92fb8d172b77e7398b3
fe3712b134068c1c25dc42e7dc908f2fa6d8aa0e

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
vebox: silence compilation warning.

Silence the following compilation warning:
  CC     i965_drv_video_la-gen75_vpp_vebox.lo
gen75_vpp_vebox.c: In function 'bdw_veb_dndi_iecp_command':
gen75_vpp_vebox.c:1537:5: warning: suggest parentheses around arithmetic in operand of '|' [-Wparentheses]

Also simplify the calculation of the VEB_DI_IECP::endingX variable
with existing helper macros.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: drop magic numbers in filters mask.

Use the existing VPP_{DNDI,IECP}_xxx flags instead of magic numbers.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: fix indication of field ordering in sequence.

VEBOX_DNDI_STATE::dndi_top_first indicates whether the top field is
first in sequence (TFF), or if the bottom field comes first. This is
an indication of the temporal sequence for input frames, available
in the "history" buffer. As such, the correct flag to check against,
from a VA-API perspective, is VA_DEINTERLACING_BOTTOM_FIELD_FIRST.

https://bugs.freedesktop.org/show_bug.cgi?id=72518
https://bugs.freedesktop.org/show_bug.cgi?id=72522

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: fix order of submitted commands.

For each frame, the Intel HD Graphics hardware specification mandates
that the following commands should be submitted, in-order: VEBOX_STATE,
VEBOX_SURFACE_STATE(input), VEBOX_SURFACE_STATE(output), VEB_DI_IECP.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: fix invalid conversion and scaling params order.

The arguments to vpp_surface_convert() were mixed up. i.e. both input
and output surfaces were reversed. Changed the vpp_surface_scaling()
arguments order as well to have more consistent helper functions.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: clean-up frame store initialization.

Rename FRAME_STORE_SUM to FRAME_STORE_COUNT, use existing macros to
determine the number of elements in the frame store array, avoid
duplicate zero initializations.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: factor out initialization of pipeline parameters.

Factor out initialization and validation of pipeline parameters.
In particular, introduce a new gen75_vebox_init_pipe_params() helper
function that initializes the filters mask and ensures the supplied
filters are going to be supported.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: robustify frame store surface storage allocations.

Clean-up frame store surface storage allocation, rename the helper
function to gen75_vebox_ensure_surfaces_storage() and make it more
robust to allocation errors. i.e. propagate them up right away.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: factor out deinterlacing code.

Completely rework the VEBOX code to factor out and improve the various
deinterlacing algorithms in particular. Introduce temporary variables
that are going to be live for the current VPP processing call.

Drop MADI/MCDI support for now.

Initial focus was to definitively fix first vs. second field detection
code, thus allowing more multiple VEBOX calls with an additional format
conversion away.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: add support for advanced deinterlacing.

Reintegrate Motion Adaptive Deinterlacing (MADI) and Motion Compensated
Deinterlacing (MCDI) support. This is totally reworked so that to allow
for bob-deinterlacing if no previous frame was supplied, improve global
robustness, and ensure that the right surface storage are used.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: use Y-tiling for internal VEBOX surfaces.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
vebox: use Y-tiling for output VEBOX surfaces.

FIXUP 0f77edc.

Always prefer tiled surfaces for performance reasons.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>