ARM: mm: Avoid the use of r8 register in cache flush all/level apis.

Currently cache_flush_by_level API is called from __v7_setup.
At this point, r8 contains the initial TTBR1 base address.
But r8 is not saved/restored in the API, resulting in corrupting
it. So when the corrupted r8 is used further during the
boot sequence, causes weird issues.

The issue becomes evident when the ARM workaround to use
"TTBR1 instead of reserved ASID during the context switch"
is applied.

Fixing this by optimising the code to avoid using r8.

Also there was a issue with optimise patch corrupting r3.
This has no functional impact, but resulted in unnessecary
cmp instructions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>