cappuccino/lsu: perform stores to cache during cache inhibit

To keep the cache memory coherent under the situation
where a system writes to a cache-inhibit memory area
while the dmmu is on, but reads from it when it is off,
writes have to go through to the cache in case of a hit.
cappuccino: move reading of rf port A to decode

The benefit of this is that it makes it possible to add an extra
registering stage between decode and execute, avoiding some
critical paths that comes from adding a lot of logic straight to
the rf RAM outputs.

This also allows for the PIPELINED multiplier to hook up
to the outputs at decode stage, to be able to add an extra
registering stage to the end of that.

The disadvantage is that extra forwarding logic is
needed between decode and execute.
cappuccino/decode: fix PIPELINED multiplier interlocks

ctrl_to_decode interlock needs to cover both port a and b
cappuccino/fetch: latch rf address on bus_access_done

Since the pipeline is advanced on this signal, the register
file gating should follow that.
cappuccino/decode: make branch indicate signal more lightweigth

decode_bubble_o is a very heavy weight signal to depend on,
the only time decode_bubble_o can be asserted when there
is a branch instruction in decode stage is when there is
either an instruction in ctrl/mem stage or execute stage
producing a result that is needed by the branch.

Explicitly use that condition in the branch_to_reg signal.
cappuccino: move overflow disable to execute_alu

This will set the originating signals to zero when
FEATURE_OVERFLOW is "NONE".
make carry flag optional with FEATURE_CARRY_FLAG

The carry flag (SR[CY]) is mandatory by the spec, but
is rarely used by software.
This makes it possible to disable the support for it to
save resources and untangle some potential critical paths.

Currently only cappuccino actually disables the support upon
setting the FEATURE_CARRY_FLAG parameter to "NONE".
cappuccino/lsu: decouple storebuffer from external bus

Instead of exposing the store buffer directly to the external
bus, add an extra registered stage.
This will add a one-cycle latency on the first write when
emptying the store-buffer, but will at the same time
remove critical paths.

This should also make disabling the store buffer all together
more straight forward, but the work to make that possible is not
done here.
cappuccino/lsu: stay in WRITE state on store_buffer_write

Apart from being one clock cycle faster, this also avoids connecting
the (potentially critical) dbus_ack_i signal to the read enable
input of the store buffer.

In addition to that it also fixes a bug where the lsu_valid
signal would be detached from the storebuffer logic when
the state machine would transition from WRITE->IDLE->WRITE.
lsu: reset state for write pending

Define the store_buffer_write_pending signal to be low after reset.
lsu: add missing signal definition

dc_refill_req was not properly defined if the cache is deactivated.
cappuccino/ctrl: do not copy FO from esr on rfe

The FO (fixed one) bit should always be set to one,
allowing it to be altered through esr is not allowed.
simple_dpram_sclk: change "TRUE"/"FALSE" parameter logic to 1/0
simple_dpram_sclk: add read enable logic

All users are also updated with a tied to 1'b1 signal
store_buffer: remove redundant fifo_raddr signal

This extra signal serves no purpose but to make the code harder
to read, connect read_pointer directly to raddr instead.
store_buffer: use re logic of ram instead of registering fifo_dout

Since the RAM already is keeping it's output data registered,
it's more area efficient to take advantage of this than
registering it in the store buffer.
Thanks to Florent Kermarrec for reminding me about this.
rf: use mor1kx_simple_dpram_sclk instead of rf_ram

With the addition of a read enable signal to
mor1kx_simple_dpram_sclk, it can act equivalent to rf_ram.
Swap all users of mor1kx_rf_ram and delete the module.
execute_alu: optimize barrel shifter

Instead of doing the actual shift operation seperately for each
shift/rotate operation, bit-reverse left shifts and only perform
a right shift.
The difference betweeen SRA, ROR and SRL is handled by
calculating a OPTION_OPERAND_WIDTH-bit word that is shifted
in from the most significant side of the result.
mor1kx_store_buffer: avoid unnecessary subtractor
change module definitions to verilog 2001 style