addac2: 250Mhz clock for signal tap added
scu_diob: 250Mhz clock for signal tap added, update scu_diob.vhd
diob: code update
diob: code update
added fg900.770+780
fg sw: fixed fg base adresses
fg sw: programm now runs the fg macros (in testmode) and has swi
scu sw: removed printfs, added debug code
scu_sw: added mil test routines
scu_sw: changes to sw, so the FG starts synced
scu_sw: enabled compile for fg sw again
fg: changes to datapath to make it start synced
update submodule pointers
mil: changed 6408 from tdf to vhdl
addac2: 250Mhz clock for signal tap added
make some documentation
addac: 250Mhz clock for signal tap added
diob: diob-board-test and code update
scu2: corrected ram size in Makefile
fg sw: programm now runs the fg macros (in testmode) and has swi