scripts/*: add missing scripts and cosmetic changes
Merge branch 'devel'
Merge branch 'devel'
Merge remote-tracking branch 'origin/devel'
hdl/*/position_calc/*: add artix 7 support
hdl/*/wb_un_cross/*: fix generated switching clock and add debug signals
hdl/*/position_calc/Manifest.py: fix syntax error
hdl/platform/artix7/*: add artix7 cores
hdl/modules/position_calc/*/artix7/*: cleanup some files
hdl/modules/position_calc/*: fix reset logic

This was causing the clokc enable signal to be desynchronized
with the corresponding clock
hdl/modules/*: add more pipeline stages in clock enable net

This is supposed to help in reducing the fanout of the net
and avoid failing timing analysis
hdl/*/generated/virtex6/*: (1/5) some fixes and enhancements

This patch introduces the following changes
and enhancements:

* Add valid signal for qualifying position
  data at all rates

* Fix off-by one bug caused by the multiplexing module
  (TDM), due to a registering stage

* Improved amplitude of CIC blocks outputs. Now we use full
  precision and manually truncate and round to the target
  number of bits

* Enhanced Monitoring chain by removing unnecessary delays

* Change Delta-Sigma modules to use Radix2 divider algorithm
  instead of High-Radix. We got a roughly decrease of 99 (11 per
  divider) in DSP48 usage blocks
hdl/*/position_calc/position_calc.vhd: (2/5) some fixes and enhancements

Change wrapper module to match new set of valid signals
hdl/*/wb_position_calc/*: (3/5) some fixes and enhancements

Add new set of valid signals and implement set of FIFOs
to cross the fs_clk2x to fs_clk domain safely by using
async fifos.

Also, it is easier to use position data at any rate now by
simply checking the valid signal. Although the usage of the set of
Clock Enable (CE) signals would be beneficial from the timing
point of view, as multi-cycle constraints would apply.
hdl/modules/dsp_cores_pkg.vhd: (4/5) some fixes and enhancements

Add new interface of all modules to match the declaration
models/*: (5/5) some fixes and enhancements

Add modified sysgen models with the fixes described in
an earlier commit
hdl/modules/wb_position_calc/*: removed .ucf file

This was causing error on designs that included dsp-cores,
but did not used the wb_position_calc module. Now the .ucf file
is kept here as a reference (as a .txt file), but it should be
coied to your top folder design and added as a .ucf file
hdl/modules/wb_un_cross/*: fix bpm_swap reset interface

This signal was missing the last commits
hdl/modules/position_calc/*/virtex6: major bug fix

This patch fixes a major bug introduced in the last
big change (from commit f809ea80e0 to commit 843c8ceb4f).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.
hdl/modules/position_calc/*/artix7: add artix7 files and major bug fix

This introduces the latest changes from commit
f809ea80e0 to commit 843c8ceb4f to artix7 FPGAs.

This patch also fixes a major bug introduced in the last
big change (f809ea80e0 to commit 843c8ceb4f).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.