ASoC: WM8804: MCLK_DIV to be set by set_clkdiv rather than within set_pll

This change allows one to deal with any conflicts which
can arise as MCLK_DIV is in the path for the TX clock,
but not the RX (it takes the pll output directly).

Change-Id: If0170d35568b75c47a30163bfb747ad202f7cad4
Signed-off-by: Douglas MacFarlane <douglas.macfarlane@wolfsonmicro.com>
ASOC: RPi: Set WM8804 MCLK_DIV=0 (256fs)

Avoids any issues with PLL setup whilst switching between
RX and TX modes

Signed-off-by: nikesh <Nikesh.Oswal@wolfsonmicro.com>
config: add config for wolfson audio card

Signed-off-by: nikesh <Nikesh.Oswal@wolfsonmicro.com>
ASOC: BCM2708: Update pcm hw info flag

Signed-off-by: nikesh <Nikesh.Oswal@wolfsonmicro.com>
ASoC: arizona: An OUTDIV of 1 is not valid, avoid this

One is not a valid value for the OUTDIV start searching at 2 instead.

Change-Id: Ibeda365afbe7f25778da7f3c185e474a5565200c
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
ASoC: arizona: Disable AIF TX/RX before configuring it

If we don't disable the AIF TX/RX then we may fall into a
situation where the new AIF settings are ignored by the device.

For example, this problem manifests when switching between
different sample rates.

Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>