nl80211: vendor command support

Add support for vendor-specific commands to nl80211. This is
intended to be used for really vendor-specific functionality
that can't be implemented in a generic fashion for any reason.
It's *NOT* intended to be used for any normal/generic feature
or any optimisations that could be implemented across drivers.
Currently, only vendor commands (with replies) are supported,
no dump operations or vendor-specific notifications.
Also add a function wdev_to_ieee80211_vif() to mac80211 which
is needed for mac80211-based drivers wanting to implement any
vendor commands.

Change-Id: Ic4729180ea31b39e7313633f216a06b96a29ee39
CRs-fixed: 576020
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: ad7e718c9b4f717823fd920a0103f7b0fb06183f
Git-repo: https://git.kernel.org/cgit/linux/kernel/git/linville/wireless-next.git
Signed-off-by: Leo Chang <leochang@codeaurora.org>
nl80211: support vendor-specific events

In addition to vendor-specific commands, also support vendor-specific
events. These must be registered with cfg80211 before they can be used.
They're also advertised in nl80211 in the wiphy information so that
userspace knows can be expected. The events themselves are sent on a
new multicast group called "vendor".

Change-Id: I184aaa9f9e8461aee572f7d0a35916cd668c2218
CRs-fixed: 576020
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: 567ffc3509b2d3f965a49a18631d3da7f9a96d4f
Git-repo: https://git.kernel.org/cgit/linux/kernel/git/linville/wireless-next.git
Signed-off-by: Leo Chang <leochang@codeaurora.org>
msm: krait-regulator: handle efuse differences

Scaling factor version is valid for
- 8974 based devices when the version bits read 1
- 8974pro based devices when the version bits read 1 or 2
- 8084 based devices when the version bits read 0
- 8092 based devices when the version bits read 0

Moreover the three bit scaling factor data for
- 8974 based devices starts at bit 16
- 8974pro based devices starts at bit 16
- 8084 based devices starts at bit 14
- 8092 based devices starts at bit 14

Update the code to handle these differences.

CRs-Fixed: 614657
Change-Id: I30c65026341ece9a03f88514127b563417df46ee
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
wcnss: Retry PIL on error ready timeout

When the first PIL on wcnss fails; and when it times out on smp2p
error ready, retry PIL a couple more times. We have seen instances where
wcnss does bootup on PIL retry.

CRs-Fixed: 613487
Change-Id: I92569559cb8022c831036ec50ccf2e7475f0278c
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
msm: mdss: Return suspend without delay in NOTIFY UPDATE

NOTIFY_UPDATE returns Suspend after 4 seconds delay.
Delay would cause HISTOGRAM_STOP ioctl to be called late.

Return suspend case without setting timer for no delay.

Change-Id: I356086de96cab85cd203bf1ad529ecf0b3bbfce3
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Allow writeback panel to start overlay during handoff

There is no longer a need to delay the hardware initialization for WB.
Previously, iommu attach was done automatically in overlay_start,
which caused page faults. However, now the iommu is attached at the same
time as continuous splash handoff, which prevents any unwanted page
faults.

Change-Id: I79f021da1ada7e342b9db84167032df5ac840e4e
Signed-off-by: Benet Clark <benetc@codeaurora.org>
wcnss: Correct the logging sequence of certain registers

PMU_PLL_STATUS and PMU_CPU_AHB_CFG_RCGR registers should be dumped
despite common_ss being collapsed.

CRs-fixed: 615461
Change-Id: Iac7da726ad70420d29411e0c9f6bcd75c776ba50
Signed-off-by: Yue Ma <yuem@codeaurora.org>
wcnss: Add MCU debug registers to the register dump list

When firmware crashes happen, add the support to log MCU registers for
debugging purpose.

CRs-fixed: 613889
Change-Id: I8f1d4f9a26912151de2594f41ac8e09648650ff2
Signed-off-by: Yue Ma <yuem@codeaurora.org>
msm_serial_hs: Dynamic allocation of port structures

This patch allocates the msm_hs_port structures
dynamically during probe and cleans up during exit.
The msm_hs_get_uart_port function now looks up the
uart_state data structure to find the right uart_port.

Change-Id: I3876959eb41173d2115d2c1acfc612b75ca2e46a
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
msm_serial_hs: Implement driver functionality to be closer to HW spec

Implement TX callflow to be in accordance with HW spec and make
sure TXEMT clock off logic is correct. On receiver side, issue
force stale interrupt and make sure upper layer get bytes upto
size of RX buffer

CRs-Fixed: 575119
Change-Id: Iee469b0ba489386b571a86897b62eae84ff34ca5
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm_serial_hs: Defensive checks

Add defensive checks in the APIs exposed to clients
and tty layer to avoid unclocked access

CRs-Fixed: 593860
Change-Id: Ibb80b18143a3b90156a7043fd66d4097f7c073e1
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
msm_serial_hs: Manage clock path-vote correctly

clock path vote is needed for core and iface vote,
so remove it after these votes are removed, and
make sure clock path vote/unvote are balanced by
removing unnecessary clock path vote

CRs-Fixed: 606403
Change-Id: I2ca2ef1cac3f0aacb7d21eb4da8bed3d39e0158c
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm_serial_hs: Avoid RX getting stuck during rapid clock on/off

Due to race conditions in clock off and clock on sequence
BAM RX descriptor doesn't get queued or may get queued multiple
times. These issues may showup when the client issues rapid clock-on
clock-off operations.
This patch optimizes clock-off sequence while synchronizing clock
off/on with the BAM RX callback (In BAM RX callback, Forcestale
is not issued for every BAM RX callback).

CRs-Fixed: 601140
Change-Id: I882bb57b597f5789daa5fef33a4bc8da174110d0
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm_serial_hs: Program RFR to synchronize clock-off sequence with HW

Assert the RFR line during clock off and de-assert
it after the clock off is successful. This is to avoid
the data to be coming from the client during clock off.

Change-Id: I6cad22a63ebd3cfaa20c52445584829b382b7e3a
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm: kgsl: Ensure that power constraints run for a full interval

Make sure that a power constraint is given a full DCVS interval to
influence the GPU before having it adjusted back down

Change-Id: Ic0dedbad22e74ce6e62e26c386b900442d7bab40
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: mdss: remove panel type check for split display case.

Split display flag is derived from dsi controller configuration
specified at dtsi. Therefore no need to add checking panel
type at FB registration.

Change-Id: I5b60656c1f5724bdc358d743b8d7600d5beba0b3
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
ARM: dts: msm: Add support for JDI dual-dsi QHD video mode panel

Add JDI dual dsi video mode panel related dtsi files.

Change-Id: I0a8103d665a96aaa6ecf62d610cffb7fb2c75b2d
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
ARM: dts: msm: Add support for JDI Dual DSI QHD cmd mode panel

Currently, only JDI Dual DSI panel is supported in video mode.
Add support for the panel to operate in command mode as well.
This can be enabled using the fastboot parameter as well.

Change-Id: Ie52243a4a83af38a09b9677601358301241eab2d
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: mdss: Do not program DSI PLL registers from DSI controller

MDSS DSI driver currently programs certain DSI PLL registers as
part of the DSI PHY off sequence. This is incorrect and could
lead to some unexpected errors such as DSI PLL getting turned off
while the branch clocks are still on. Fix this by removing all
such register programming.

Change-Id: Ie1e88cd18de6b8ef8804f7a2b34b8b8282166c96
CRs-Fixed: 509801
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: mdss: dsi-1 as master clock controller at split display case

During split display case, both dsi controllers share the same
dsi pll(dsi0) dsi-0 clock need to be enabled before dsi-1 and disabled
in the reverse order. This mechanism helps using a unified clock control
logic.

Change-Id: I9fe0095b0427c9c2b7fd84c3179bc8364049cce4
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>