vhdlpp: Minor code cleaning.
vhdlpp: Added basic support for concatenated expressions.
vhdlpp: Emit '-' std_logic value as 'x'.

Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
vhdlpp: Fix error message for 'right attribute.
vhdlpp: Emit use_types in Architecture.
vhdlpp: Support for integer() function.

Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd)
Real numbers are rounded, this is compatible with ModelSim behavior.
Merge pull request #47 from orsonmmz/concat

Expression concatenation in VHDL