Local: ARM: shmobile: r8a7790: Remove duplicate audio DMA initialization

Commit 556090d ("Local: ARM: shmobile: r8a7790: enable DMA for DT")
added audio DMA initialization calls to r8a7790_add_dt_devices(),
but forgot to remove them from r8a7790_add_standard_devices().

As r8a7790_add_standard_devices() calls r8a7790_add_dt_devices(), they're
now executed twice.

Based on a similar change for the r8a7791 by
Geert Uytterhoeven.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: fix executability of CMA mappings

The CMA region was being marked executable:

0xdc04e000-0xdc050000           8K     RW x      MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW x      MEM/CACHED/WBRA
0xdc4f5000-0xdc500000          44K     RW x      MEM/CACHED/WBRA
0xdcce9000-0xe0000000       52316K     RW x      MEM/CACHED/WBRA

This is mainly due to the badly worded MT_MEMORY_DMA_READY symbol, but
there are also a few other places in dma-mapping which should be
corrected to use the right constant.  Fix all these places:

0xdc04e000-0xdc050000           8K     RW NX     MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW NX     MEM/CACHED/WBRA
0xdc280000-0xdc300000         512K     RW NX     MEM/CACHED/WBRA
0xdc6fc000-0xe0000000       58384K     RW NX     MEM/CACHED/WBRA

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 71b55663c5d0a6f8473045db1c8b376803780191)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Revert "mtd: xilinx: merge nand flash support from xilinx repository"

This reverts commit ac13930f7d4a0648c711ae08e523e6cf42da54e8.
mtd: m25p80: use spi_get_drvdata() and spi_set_drvdata()

Use the wrapper functions for getting and setting the driver data using
spi_device instead of using dev_{get|set}_drvdata with &spi->dev, so we
can directly pass a struct spi_device.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 975aefc9de7ab893e9e784ec52cf97e1827259da)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: utilize dedicated 4-byte addressing commands

Traditionally, the command set used by SPI flash only supported a 3-byte
address. However, large SPI flash (>= 32MiB, or 256Mib) require 4 bytes
to address the entire flash. Most manufacturers have supplied a mode
switch (via a "bank register writer", or a "enable 4-byte mode"
command), which tells the flash to expect 4 address cycles from now on,
instead of 3. This mode remains until power is cut, the reset line is
triggered (on packages where present), or a command is sent to reset the
flash or to reset the 3-byte addressing mode.

As an alternative, some flash manufacturers have developed a new command
set that accept a full 4-byte address. They can be used orthogonally to
any of the modes; that is, they can be used when the flash is in either
3-byte or 4-byte address mode.

Now, there are a number of reasons why the "stateful" 4-byte address
mode switch may not be acceptable. For instance, some SoC's perform a
dumb boot sequence in which they only send 3-byte read commands to the
flash. However, if an unexpected reset occurs, the flash chip cannot be
guaranteed to return to its 3-byte mode. Thus, the SoC controller and
flash will not understand each other. (One might consider hooking up the
aforementioned reset pin to the system reset line so that any system
reset will reset the flash to 3-byte mode, but some packages do not
provide this pin. And in some other packages, one must choose between
having a reset pin and having enough pins for 4-output QSPI support.
It is an error prone process choosing a flash that will support a
hardware reset pin!)

This patch provides support for the new stateless command set, so that
we can avoid the problems that come with a stateful addressing mode
change. The flash can be left in "3-byte mode" while still accessing the
entire flash.

Note that Spansion supports this command set on all its large flash
(e.g, S25FL512S), and Macronix has begun supporting this command set on
some new flash (e.g., MX25L25635F). For the moment, I don't know how to
differentiate the Macronix that don't support this command set (e.g.,
MX25L25635E) from those that do, so this patch only supports Spansion.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 87c9511fba2bd069a35e1312587a29e112fc0cd6)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: correct EN4B/EX4B comment

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit caddab0f5b7563db72640e6c6a21fd7076418f36)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: devices: added the 16MiB winbond device

Added a 16MiB winbond devce to the device list
erase size = 64KiB and number of blocks = 256.

Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 4b6ff7afe8ca356ac51e98a7e01997cc17669254)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: devices: use dev_get_platdata()

Use the wrapper function for retrieving the platform data instead of
accessing dev->platform_data directly.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 0278fd3fa34fb029e40224dd83d2628254f45481)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressing

For SPI NOR flash that are larger than 128Mbit (16MiB), we need 4 bytes
of address space to reach the entire flash; however, the original SPI
flash protocol used only 3 bytes for the address. So far, the practice
for handling this has been either to use new command opcodes that are
defined to use 4 bytes for their address, or to use special
mode-switching command to configure all traditionally-3-byte-address
commands to take 4 bytes instead.

Macronix and Spansion developed two incompatible methods for
entering/exiting "4-byte address mode." Micron flash uses the Macronix
method (OPCODE_{EN4B,EX4B}), not the Spansion method.

This patch solves addressing issues on Micron n25q256a and provides the
ability to support other future Micron SPI flash >16MiB.

Quoting a Micron representative:

  "Majority of our NOR that needs 4-byte addressing (256Mb or 32MB and
   higher) enter and exit 4byte through B7h and E9h commands. The
   N25Q256A7xxx and N25Q512A7xxx parts do not support 4-byte addressing
   mode via B7h or E9h command."

They further clarified that those that don't support the enter/exit
opcodes (B7h/E9h) are manufactured specifically to come up by default in
4-byte mode. We don't need to treat those parts any diffently, as they
will discard the EN4B opcode as a no-op.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit eedeac3ce94e2a3d4ff28974221b9f309358d8de)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: remove unnecessary ifdef

of_property_read_bool properly compiles away, no need to ifdef this
for non DT builds.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 8f229fb8566dd58004a84e2644c1f88ebe71bb88)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: Pass flags through CAT25_INFO macro

The flags may have to be overwritten, so add them to the CAT25_INFO
macro.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 7e7d83b32ed7094f73008a99db4fecb74b8c2099)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: make CONFIG_M25PXX_USE_FAST_READ safe to enable

This patch adds a flag to struct flash_info indicating that
fast_read is not supported. This now gives the following logic
when determing whether to enable fastread:

If the flash chip does not support fast_read, then disable it.
Otherwise:
1) enable fast_read if device node contains m25p,fast-read
2) enable fast_read if forced in Kconfig

This makes enabling CONFIG_M25PXX_USE_FAST_READ a safe option
since we no longer enable the fast_read option unconditionally.

For now fast_read is disabled for the everspin mr25h256 and the
catalyst devices. Others may need the flag aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit 58146992c956c2104ca8990a621e39a20e9c9f94)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: add support for mr25h10

This adds support for the Everspin mr25h10 MRAM chip to the m25p80
driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
(cherry picked from commit a3d7ee9ff80949e8786072eaf0b267499aec3d05)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: chips: Add support for PMC SPI Flash chips in m25p80.c

Add support for PMC (now Chingis, part of ISSI) Pm25LV512 (512 Kib),
Pm25LV010 (1 Mib) and Pm25LQ032 (32 Mib) SPI Flash chips.

This patch addresses two generations of PMC SPI Flash chips:

 - Pm25LV512 and Pm25LV010: these have 4KiB sectors and 32KiB
   blocks. The 4KiB sector erase uses a non-standard opcode
   (0xd7). They do not support JEDEC RDID (0x9f), and so they can only
   be detected by matching their name string with pre-configured
   platform data. Because of the cascaded acquisitions, the datasheet
   is no longer available on the current manufacturer's website,
   although it is still commonly used in some recent wireless routers
   (<https://forum.openwrt.org/viewtopic.php?pid=186360#p186360>). The
   only public datasheet available seems to be on GeoCities:
   <http://www.geocities.jp/scottle556/pdf/Pm25LV512-010.pdf>

 - Pm25LQ032: a newer generation flash, with 4KiB sectors and 64KiB
   blocks. It uses the standard erase and JEDEC read-ID
   opcodes. Manufacturer's datasheet is here:
   <http://www.chingistek.com/img/Product_Files/Pm25LQ032C%20datasheet%20v1.6.1.pdf>

This patch is resent in order to take into account both Brian Norris
remarks and this upstream patch:

commit e534ee4f9ca29fdb38eea4b0c53f2154fbd8c1ee
Author: Krzysztof Mazur <krzysiek@podlesie.net>
Date:   Fri Feb 22 15:51:05 2013 +0100

    mtd: m25p80: introduce SST_WRITE flag for SST byte programming

    Not all SST devices implement the SST byte programming command.
    Some devices (like SST25VF064C) implement only standard m25p80 page
    write command.

    Now SPI flash devices that need sst_write() are explicitly marked
    with new SST_WRITE flag and the decision to use sst_write() is based
    on this flag instead of manufacturer id.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
[Brian: fixed conflict]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

(cherry picked from commit 6c3b88970175e18a67eb8e55c4eba10614d0d5dc)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: Fix 4 byte addressing mode for Micron devices.

According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte
addressing mode should be entered as follows:

<quote>
To enter or exit the 4-byte address mode, the WRITE ENABLE command
must be executed to set the write enable latch bit to 1. (Note: The
WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and
N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the
command is immediate; after the command has been executed, the write
enable latch bit is cleared to 0.
</quote>

Micron's portable way to perform this for all types of Micron flash
is to first issue a write enable, then switch the addressing mode
followed by a write disable to avoid leaving the flash in a write-
able state.

Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com>
[Brian: reworked a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

(cherry picked from commit 2b468ef0e7959b703626b64c4d264ef822c9267a)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: Add support for ESMT F25L32PA

This flashchip is used in D-Link DIR-610 A1 router board
and maybe several others, yet is not kernel upstream.

So add support for it according to datasheet [0], making it easier
to support other boards using this flashchip in the future.

[0] http://www.esmt.com.tw/DB/manager/upload/F25L32PA.pdf

Signed-off-by: Flavio Silveira <fggs@terra.com.br>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit e6db7c8484187f8bf6012cbc700f7b62cdc809be)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: Add support for Micron N25Q512A memory

Micron N25Q512A is a spi flash memory with following features:
-64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory.
-Memory is organised as 1024(64KB) main sectors.
-Each sector is divided into 256 pages.
-Register set/Opcodes are similar to other N25Q family products.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 867f770de8127d2e1dd730ce60608dfdac08d863)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: fix allocation size

This patch fixes two memory errors:

1. During a probe failure (in mtd_device_parse_register?) the command
   buffer would not be freed.

2. The command buffer's size is determined based on the 'fast_read'
   boolean, but the assignment of fast_read is made after this
   allocation. Thus, the buffer may be allocated "too small".

To fix the first, just switch to the devres version of kzalloc.

To fix the second, increase MAX_CMD_SIZE unconditionally. It's not worth
saving a byte to fiddle around with the conditions here.

This problem was reported by Yuhang Wang a while back.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reported-by: Yuhang Wang <wangyuhang2014@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Cc: <stable@vger.kernel.org>
(cherry picked from commit 778d226a1462572b51d6777cdb1d611543410cb4)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: remove obsolete FIXME

The FIXME and NOTE have already been fixed (we have FAST_READ support).

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 1a874e91018ea99d7f012a0824669aa9ed833d6f)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
mtd: m25p80: re-align ID entries

No change in the table data.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
(cherry picked from commit 6e5d9bda27000c682a9b38f0466941007e295f82)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>