Adding self-made uart_send.v and uart_send_test.v
Adding project file created by me and topmodule.ucf not created by me
 gitignore files generated by IDE
Make uart_send.v even shorter.
turn uart_send_test.v into a self-checking test
small comment fix
UART receiver + test
counter.v
add missing baud.v
shortening of uart_send_test.v
uart komplex test + bugfixes + clk_wiz_v3_6.v
gitignore programming file related files
counter.v: make output VALUE non-reg
topmodule.v: Test UART (echo)
uart sending sequence works ok
gitignore some more
3 STOP bits and remove fancy clock from toplevel
get rid of warning in counter.v
remove header comment from toplevel_test.v
remove baud.v and clk_wiz_v3_6.v
slew fast for uart txd
lowercase internal signal
fix test (remove removed debug signal)
wire->localparam