give CPU and VIC-IV modules more appropriate file names.
complete renaming of VIC-IV and GS4510 CPU modules.
fix bug with ESC sequence handling.
begin work towards command history in serial monitor.
import version of Ophis with 4510 support.
debug and formatting changes.
implement TRB and TSB
begin implementing BBS/BBR instructions.
Fix incorrect initialisation of B register. ISsue #25
debugging BBS/BBR instructions and ghdl simulation problems.
Issue #25
reduce number of compilation warnings.
promote phi0 clock for CIAs to be independent of CPU speed.
similarly make PS2 clock independent of CPU speed.
Add B register to serial monitor register display.
Fix VIC/non-VIC fastio mux selection.
other misc fixes.
remove some synthesis warnings.
correct commentary on 50/60hz
fix mux selection of VIC/non-VIC IO.
Begin preparing for i-cache.  Issue #29
remove unused signal.
more work towards i-cache. Issue #29
try fixing colour ram reading bug by presenting colour ram
read data separately to the CPU.
move to booting from kickstart ROM.  Remove basic and kernel ROMs.
Issue #30.
make kickstart memory mapping override all else.
allow slowram to map to $0020000-$003FFFF for C65 ROM emulation.
Issue #30.
add kickstart.vhdl to ISE project. Issue #30.
control colour ram CS line from CPU to get rid of write glitches.