target-arm: A64: Add SIMD modified immediate group

This patch adds support for the AdvSIMD modified immediate group with
all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <agraf@suse.de>
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

v2 -> v3:
  - use extract32/sextract32 instead of get_bits and get_sbits
v3 -> v4 (ajb):
  - new decoder structure
  - port fixes from Matz tree (including from Julian Brown <julian@codesourcery.com>)
  - return before allocating tcg regs (leak)
  - reduce usage of temps
  - rename op to rd and rd_hi
  - use helper functions for fp offset
  - don't do pointless quad ops
  - fix bug with imm setup (risu)
  - move shift, i into block
  - added AdvSIMDExpandImm commentary
  - rm pointless shift calculation
v4 -> v5 (ajb):
  - move shift, i down into more local blocks
  - change cmode>>1 & pattern to use cmode_3_1
  - cmode_0 convenience variable
  - fixup ULL usage
  - slightly more optimal tcg_rd_hi code
v5 -> v6 (ajb)
  - fix whitespace errors
  - rebased onto new decode layout
v6 -> v7 (pmm)
  - fix busted diagram
  - check o2 unallocated case
  - loop rather than is_q checks
  - minor checkpatch nit fixes
target-arm: A64: support for AdvSIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions:

  * do_vec_ld
  * do_vec_st

Which don't zero extend like the fp variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 -> v3:
   - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):
   - move into new decoder structure
   - use new API for loading temp addr
   - push various variables to local blocks
   - fix semantics of clearing V reg on load
   - tested with risu

v4 -> v5 (ajb):
   - catch more unallocated values
   - add missing returns
   - use do_fp_ld for offset==0 instead of explicit clear_reg
target-arm: A64: support for SIMD GPR copy (INS&DUP)

This adds support for the GPR->Vector forms on INS and DUP. These were
loosely based on the SUSE originals but are now considerably simpler.
They also re-factor the vec ld/st functions and add the helpers:

* do_vec_set
* do_vec_get

Which are used to extract/set subsets of the Vector registers. They take
a register id and an offset.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   - use ctz32 instead of hand-rolled bit finder
   - catch additional size > 3 unallocated
   - merge INS and DUP into one commit

v5 (ajb):
   - conflicts on re-base
target-arm: A64: support for SIMD copy (remaining ops)

This adds the element forms of INS/DUP as well as the SMOV/UMOV
operations. This was taken from a merge and fix-up of patches in the
Matz tree.

---

v1 (ajb):
   - merge remaining cases from Matz tree
   - catch all unallocated
   - fix get_bits->extract32
   - ensure sign extension correct for !is_q
target-arm: A64: Add SIMD scalar 3 same ADD/SUB

This adds just Scalar ADD/SUB support to the SIMD scalar 3 same group.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   - catch Reserved Values
   - don't bother looping, it's just a single D op
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
rm unused field
scripts/qemu-binfmt-conf.sh: re-factor and clean-up

I was looking to set-up for development but found the script made some
hard-coded assumptions. It doesn't seem the script is used by the
distros but if it had a little more love maybe it would be ;-)

* Add usage() instructions
* Move all registering to a single function
* Check for existence of executable qemu before registering
* Add -d (devel) mode for subscribing in-src tree binaries
* error handling when setting binfmt fails
* add support for aarch64
scripts/qemu-binfmt-check.py: a binfmt checker

This script allows you to check if a given binary will match against any
of the currently registered binfmts on the system.
start of simd ldst single structure decode

It's just a stub for now
linux-user: Implement sendmmsg syscall

Glibc when built for newer kernels assumes that the sendmmsg syscall is available.
Without it, dns resolution simply fails to work.

Wrap the syscall with existing infrastructure so that we don't have a host dependency
on sendmmsg.

Signed-off-by: Alexander Graf <agraf@suse.de>