bayleybay_fsp: Add comments for the MMC/SD devices in devicetree

This just adds some additional comments for the EMMC / SD / SDIO PCI
devices in devicetree.

The documentation states that the EMMC 4.1 device shouldn't be used,
but it's available to enable in the FSP.  Because it can be enabled,
I've included it in the devicetree even though its use is discouraged.

Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6089
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
fsp_baytrail: Minor Kconfig updates

- remove the Kconfig text when setting the default for the FSP location.
The text was showing up twice in the config menu.

- Remove an extra 'the' in the help text.

Change-Id: I3777833bf32e19bbe5a8493578a9346d6ab062a4
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6090
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
baytrail_fsp: Fix the mmconf Kconfig

The override value in the mainboard that was removed was correct.

Change-Id: Ie820df0d6b7a713488173240f0c0ca4a9e108f71
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6095
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
MP Table: Change types to be consistent with the spec

Update the elements in the MP Spec structures with
appropriate types to more accurately reflect the
real sizes of the bit fields in the MP Tables.

Also add a function for PCI I/O interrupts since these are
handled slightly differently than the other I/O interrupt
entries.  The src_bus_irq field is defined where
 Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3
 Bits 2-6: Originating PCI Device Number
 Bit 7: Reserved

Change-Id: I693407beaa0ee454f49464e43ed45d8cba3b18fc
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/6050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
i945 boards: Drop disabled ram_check() calls

This code would not get enabled just by flipping the options in menuconfig,
also ramcheck() no longer test the range like the parameters would imply.

We should add non-destructive ram_check() on S3 resume path to verify
memory controller configuration has been properly recovered.

Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6027
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Declare acpi_is_wakeup_early() only once

Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
AGESA: Move config parameters for non-volatile S3 data

These parameters are not specific to the southbridge device, but
the implementation of S3 storage defined by CPU code.

Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6081
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
AGESA S3: Fix ACPISCRATCH in CBMEM

After commit

  2ca2afe ACPI S3 support: Add acpi_s3_resume_allowed()

ACPISCRATCH region in CBMEM was no longer allocated, causing
AGESA platforms to fail S3 resume.

IS_ENABLED() did not evaluate true here with non-zero parameter.

Also avoid multiple defined defaults for HIGH_SCRATCH_MEMORY_SIZE.

Change-Id: Id99e4bee91581b8ac3d1ec44763b2d792b721832
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6093
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
device/{cardbus,agp}.h: Missing header for device_t type

Missing header for the ramstage version of device_t which is a struct
ptr.

Change-Id: Ie2a30b75ee1d0513397276b81e8df1d995707f6f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6080
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
device/pci_device.c: Sanitize headers

Change-Id: I6254f4ab767952cc8ff31bb462c7037b027442ba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
src/console: Sanitize headers and IS_ENABLED usage

Alphabetise headers and remove any #if CONFIG_ guards around them.
Use #if IS_ENABLED(CONFIG_FOO) over #if CONFIG_FOO where applicable.

Change-Id: I2a616bcfb8470a1fa21c9e26271e81cca835272a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
src/ec: Sanitize headers and comment #endif pairings

Comment #endif /* FOO */ pairings.
Alphabetise headers and remove any #if CONFIG_ guards around them.

Background rational:
Remove guarding the inclusion of headers based on CONFIG_ options. This
*potentially* could hide issues such as functions being swapped from
under our feet, since different runtime behaviour could be declared with
the same function same name and type-signature. Hence, depending on the
header we happen to get may change runtime behaviour.

Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6059
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
drivers/elog: Unmangle header include out of pre-proc cond

Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
intel/lynxpoint: xhci: Update magic bits to new magic values

BUG=chrome-os-partner:22254
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco

Original-Change-Id: I493a8cbbfdd958b855f6b4c01e03ee524be74c6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167050
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 226a66772768bf3c2f69e585984e52c0c270821f)

Change-Id: I800b02b511f9d188dd7a8e8d83139a8181346916
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167312
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6014
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
intel/haswell: Report x32 memory as "x8 or x32"

There is only one bit for memory width reporting, either x16 or
other.  With x32 memory this code is reporting it as x8 so instead
report "x8 or x32" in this condition.

BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-coreboot-samus

Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6008
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
include/pc80/mc146818rtc.h: Move include to top of file

Change-Id: I7640186702abac6fe116e3c750be08c958bc6cad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
drivers/intel/gma: Uninitialized var before if condition

The variable 'wait' is used uninitialized whenever 'if' condition is false
                if (val & DDI_BUF_CTL_ENABLE) {
                    ^~~~~~~~~~~~~~~~~~~~~~~~

Leading to an uninitialized use occurs here:
                if (wait)
                    ^~~~

Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
nehalem sandy ivy: Check cbmem_add() result for MRC data

In theory we could run out of CBMEM space so check the entry was added.
There is no interest to support builds without EARLY_CBMEM_INIT.

Change-Id: I68dd7c20e3d3692331aaafa2a692c5c0dfce95d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6033
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
pc80/mc146818rtc.h: Has X86 specific inlines without guards

PC80 header components are winding up in ARM builds with static inline
X86 specific code.

Change-Id: Ib23e70a34c478dc099b84b59a5234539cc2482e3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
sandy/ivy boards: Switch to use DYNAMIC_CBMEM

Like with other more recent boards already using DYNAMIC_CBMEM,
the pointer to TOC is no longer stored in GNVS for ACPI.

Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>