wb_intercon: allow single master/slaves

The result of clog2(1) = 0, which will result in
master/slave_sel bit vectors of [-1:0].
Threat the special case of num_masters/slaves == 1,
so a bit vector [0:0] is created.
wb_intercon: fix multiple masters to single slave connections

The commit: 5f7cbf7e77a6d54641efc4c832628265a605d1e2
'wb_intercon: fix single slave connections'
took care of the case with a single master connected to
a single slave. The case with several masters connected
to a single slave was however oversighted.
cores/mor1kx: add mor1kx_monitor

This enables the use of mor1kx_monitor and the associated
plusargs.
systems: add mor1kx-generic

Heavily based on the or1200-generic system, the mor1kx-generic
system serves the same kind of purpose - to provide a minimal
simulation platform, but for mor1kx instead of or1200.
verilator_tb_utils: change all 'times' to uint64_t

Franck Jullien reported that unsigned long is not a valid argument
for tfp->dump() on 32-bit machines.
This changes all 'time' (cycles, really) references to uint64_t.
cores: remove name from [vpi] sections

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Update description
mor1kx: Add new LRU module for caches

The current mor1kx master has a new file for the multiple way caches.
cores: add mt46v16m16p DDR memory model

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add wb_altera_ddr_wrapper

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add ps2 core

This core is originally from opencores, but have been rewritten
in verilog and had a lot of bugfixes added to it.
Due to this, it makes more sense to add this as a whole core
instead of pulling in the original and adding the complete rewrite
as a patch.
systems: add atlys board port

OpenRISC system for Digilent Atlys development board.
Basically lifted 'as is' from the orpsocv2 port at:
git://git.openrisc.net/stefan/orpsoc

TODO:
 - Rewrite dvi_gen (currently a hacked up Xilinx whitepaper)
 - Clean up the Xilinx MIG memory controller wrapper
   (and possibly generate the MIG with coregen on fly)
 - General cleanup and de-orpsocv2-fication
Merge pull request #48 from skristiansson/verilator_tb_utils

verilator_tb_utils: change all 'times' to uint64_t
Merge branch 'atlys' of git://github.com/skristiansson/orpsoc-cores
Add wb_ram

wb_ram is a generic memory that is intended to map against on-chip RAM or registers
wb_ram: Fix broken link in README.md
or1200-generic: add debug tap anf jtag_vpi support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add csrbrg core
cores: add minimac2 core
Merge branch 'minimac2' of https://github.com/veprbl/orpsoc-cores into upstream