hdl/modules/*/wb_acq_core: add simple differente counter module

This module could be used to measure the difference between writes
from the APP and the WDF DDR3 interfaces, as we can't have more
than 2 clock cycles delay after the APP command has been issued.
See ug586, Zynq-7000 SoC and 7 Series Devices Memory Interface
Solutuions, page 156.
hdl/modules/*/wb_acq_core/*: improve DDR3 interface code

We have removed combinatorial outputs to the DDR3 memory
controller and correctly added stall signals to the previous
modules.
hdl/modules/*/wb_acq_core/wb_acq_core.vhd: fix lost start flag

Whe dealing with ext_clk slower than the fs_clk we could loose
the start flag. Now, instead of a simple FF chain we employ
a generic pulse synchronizer.