Merge "Merge "Merge "soc: qcom: smd: Validate read and write addresses"""
Merge "Merge "soc: qcom: smd: Validate read and write addresses""
Merge "Merge "Merge "soc: qcom: smd: Validate read and write addresses"""
Merge "Merge "soc: qcom: smd: Validate read and write addresses""
Merge "Merge "Merge "soc: qcom: smd: Validate read and write addresses"""
ARM: fix executability of CMA mappings

The CMA region was being marked executable:

0xdc04e000-0xdc050000           8K     RW x      MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW x      MEM/CACHED/WBRA
0xdc4f5000-0xdc500000          44K     RW x      MEM/CACHED/WBRA
0xdcce9000-0xe0000000       52316K     RW x      MEM/CACHED/WBRA

This is mainly due to the badly worded MT_MEMORY_DMA_READY symbol, but
there are also a few other places in dma-mapping which should be
corrected to use the right constant.  Fix all these places:

0xdc04e000-0xdc050000           8K     RW NX     MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW NX     MEM/CACHED/WBRA
0xdc280000-0xdc300000         512K     RW NX     MEM/CACHED/WBRA
0xdc6fc000-0xe0000000       58384K     RW NX     MEM/CACHED/WBRA

Change-Id: I044360a8f08b1a4ae3e3e9e623fb77af2b427c51
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: 71b55663c5d0a6f8473045db1c8b376803780191
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[lauraa@codeaurora.org: Context fixups due to __dma_remap signature change]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
ARM: dma-mapping: don't allow DMA mappings to be marked executable

DMA mapping permissions were being derived from pgprot_kernel directly
without using PAGE_KERNEL.  This causes them to be marked with executable
permission, which is not what we want.  Fix this.

Change-Id: Ib40f59f3c569f82409943cf8f9a86a9869d922cc
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: 0ea1ec713f04bdfac343c9702b21cd3a7c711826
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[lauraa@codeaurora.org: dropped functions not in older builds]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Merge "ARM: fix executability of CMA mappings"
Merge "ARM: dma-mapping: don't allow DMA mappings to be marked executable"
msm: krait-regulator-pmic: account for PWM_CL register security

The PWM_CL register is secure i.e. driver has to write 0xA5 to 0XD0
register to allow updates to PWM_CL register.

Fix it.

Change-Id: I3f273627bdc137d8c10768c7d5824abe96ee8707
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Merge "msm: kgsl: Add hang interrupt and change HW fault generation"
Merge "msm: kgsl: Enable hang interrupt by setting right bits for A330V2"
Merge "msm: kgsl: Enable hang interrupt for a330v2"
Merge "msm: kgsl: Increase the timeout value for fault detection"
Merge "spi_qsd: Add core message queue feature"
msm: socinfo: Add support for socinfo v9

A new socinfo format version 9 is added with support
for foundry id. Update the socinfo struct to reflect
this change.

CRs-Fixed: 645243
Change-Id: I8cfd961cd29fc8b7173650e22738db81a7069811
Signed-off-by: Kishan Kumar <kishank@codeaurora.org>
Merge "USB: Clear pm_done flag to false in msm_otg_sm_work"
mmc: core: Fix clock frequency transitions during invalid states

eMMC and SD card specifications restrict the usage of a class of
commands while commands in other class are in progress. For example,
during erase operations the SD/eMMC spec. allows only CMD35, CMD36,
CMD38. If clock scaling is enabled and decide to scale up the clocks
it may be possible that CMD19/21 tuning commands are sent in between
erase commands, which is illegal as per specification.

Fix such illegal transactions to the card and also make clock scaling
statistics accountable only for read/write commands instead of time
consuming commands, like CMD38 erase, where transactions are independent
of bus frequency.

Change-Id: Iffba175787837e7f95bde8970f19d0f0f9d7d67d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
ASoC: msm: qdsp6v2: Avoid DS1 and SRS topology on low latency path

Currently, the low latency path go through tuning of the post
processing with the default as well as third party post
processing topologies such as DS1 and TruMedia topology. Avoid
enabling the DS1 and TruMedia topology on low latency path
retaining the tuning functionality on the default topology.

CRs-Fixed: 643857
Change-Id: I8ae6b4ecb0be530c8d72218d39498cff7f8a7fd9
Signed-off-by: Subhash Chandra Bose Naripeddy <snariped@codeaurora.org>
msm: camera: sensor: Update to use wait_for_completion.

Use wait_for_completion in place of wait_for_completion_interruptible

Change-Id: I960b334128e2b811b27c64721a65f7c7e773b085
Signed-off-by: Rajesh Bondugula <rajeshb@codeaurora.org>