Merge, from trunk, r2957:
339336  PPC64 store quad instruction (stq) is not supposed to
        change the address register contents



git-svn-id: svn://svn.valgrind.org/vex@3001 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from trunk, r2960
339182  ppc64: AvSplat ought to load destination vector register with 16/16
        bytes stored prior


git-svn-id: svn://svn.valgrind.org/vex@3002 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from trunk, 2962, 2966, 2967, 2973
339433  ppc64 lxvw4x instruction uses four 32-byte loads


git-svn-id: svn://svn.valgrind.org/vex@3003 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from trunk, r2975
339858  arm64 dmb sy not implemented
2975 (subsequently overwritten by 2986)



git-svn-id: svn://svn.valgrind.org/vex@3004 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from trunk, r2976
Implement SIMD (de)interleaving loads/stores:
  LD1/ST1 (multiple 1-elem structs to/from 1 reg
  LD2/ST2 (multiple 2-elem structs to/from 2 regs
  LD3/ST3 (multiple 3-elem structs to/from 3 regs
  LD4/ST4 (multiple 4-elem structs to/from 4 regs
Also:
  LDNP, STNP  (load/store vector pair, non-temporal)



git-svn-id: svn://svn.valgrind.org/vex@3005 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from trunk, r2979
* add a missing extra m-reg check for some LD/ST vector cases 
 
* implement 
  LD1/ST1 (multiple 1-elem structs to/from 2 regs 
  LD1/ST1 (multiple 1-elem structs to/from 3 regs 
  LD1/ST1 (multiple 1-elem structs to/from 4 regs  
  LD1R (single structure, replicate)  
  LD2R (single structure, replicate) 
  LD3R (single structure, replicate) 
  LD4R (single structure, replicate) 
  LD1/ST1 (single structure, to/from one lane) 
  LD2/ST2 (single structure, to/from one lane) 
  LD3/ST3 (single structure, to/from one lane) 
  LD4/ST4 (single structure, to/from one lane) 

I believe this completes the implementation of load and store
instructions for AArch64 ARMv8.



git-svn-id: svn://svn.valgrind.org/vex@3006 8f6e269a-dfd6-0310-a8e1-e2731360e62c