OMAP4: SGX: Set DPLL PER m7x2 as source for SGX FCLK

SGX functional clock can be sourced from either CORE or PER
DPLLs and usually set to PER in the boot-loader for OMAP4.
If not set to PER, then by default gets sourced from CORE M7x2.

On OMAP4, OPP100/OPP50 freqs for SGX are 307.2/153.6 Mhz, which
can be directly derived from PER m7x2 without changing the
divider. Otherwise will be sourced from CORE m7x2 and when dvfs
layer request for 307.2/153.6Mhz will be getting  320/160Mhz.

Change-Id: Ifd3b9374f029adcdcf1bf04e570d188fea3737f3
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Vinay Chaurasia <vinaych@ti.com>

Patch Set 1