drm: platform: update moved Tegra header

Header for tegra_powergate functions has moved to soc/tegra/pmc.h.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
clk: make therm and volt devices optional

Allow the clock subsystem to operate even if voltage and thermal devices
are not set for the device (for people with watercooling! ;))

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
clk: support for non-BIOS pstates

Make nouveau_clock_create() take new two optional arguments: an array
of pstates and its size. When these are specified,
nouveau_clock_create() will use the provided pstates instead of
probing them using the BIOS.

This is useful for platforms which do not provide a BIOS, like Tegra.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
gk20a: reclocking support

Add support for reclocking on GK20A, using a statically-defined pstates
table. The algorithms for calculating the coefficients and setting the
clocks are directly taken from the ChromeOS kernel.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
HACK: drm/nouveau: prime: Pin buffer objects to VRAM

This is currently required to work around the lack of proper SMMU
support on Tegra. Ideally buffer objects could always be pinned to GART
and the SMMU will take care of mapping them to a linear I/O virtual
address range for importers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[HACK] add gk20a instmem

This is a gazillion times faster, but requires to invalidate the
GPU L2 (probably at a better place than this!)
drm/nouveau/vm: fix mapping of SG pages list

SG pages lists (not to be confused with scatterlists) are a list of 4KB
memory pages used to define a nouveau_mem. Mapping them to a VM that
does not use 4KB apertures resulted in each subsequent 4KB physical page
being mapped into a larger VM aperture, thus creating an incorrect,
overlapping mapping.

This patch fixes this issue by detecting when such mappings occur and by
skipping the required number of pages in the list to ensure a correct
linear mapping.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: map pages using DMA API

The DMA API is the recommended way to map pages no matter what the
underlying bus is. Use the DMA functions for page mapping and remove
currently existing wrappers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
drm/nouveau: introduce nv_device_is_cpu_coherent()

Add a function allowing us to know whether a device is CPU-coherent,
i.e. accesses performed by the CPU on GPU-mapped buffers will
be immediately visible on the GPU side and vice-versa.

For now, a device is considered to be coherent if it uses the PCI bus on
a non-ARM architecture.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: implement explicitly coherent BOs

Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which
means that we want the allocated BO to be perfectly coherent between the
CPU and GPU. This is useful on non-coherent architectures for which we
do not want to manually sync some rarely-accessed buffers: typically,
fences and pushbuffers.

A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent
architecture will be populated using the DMA API, and accesses to it
performed using the coherent mapping performed by dma_alloc_coherent().

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: synchronize BOs when required

On architectures for which access to GPU memory is non-coherent,
caches need to be flushed and invalidated explicitly when BO control
changes between CPU and GPU.

This patch adds buffer synchronization functions which invokes the
correct API (PCI or DMA) to ensure synchronization is effective.

Based on the TTM DMA cache helper patches by Lucas Stach.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: allocate GPFIFOs and fences coherently

Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to
allow them to be safely accessed by the kernel without being synced
on non-coherent architectures.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>