code generation for registers and toplevel I/O
no tests but. code generation.
Merge remote-tracking branch 'public/master' into issue120-vhdl-codegen
Merge branch 'issue119-simple-drc' into issue120-vhdl-codegen
log4j downgrade to 1.2
add simple test case for output product
Merge branch 'master' into issue120-vhdl-codegen
add newlines to entity, ports
code generation fix for top-level input nets
code gen fixes for registers
checkstyle fixes
remove unused junit dependencies
Merge pull request #133 from mtrberzi/issue120-vhdl-codegen

VHDL code generation: nets, registers
Initial deserialization code

For murphy :)

Currently only support types, will move to support actual values...
soon(tm) (hopefully tomorrow).

There is a bit of awkwardness WRT how field names are used, since there
this is pure object construction instead of using reflection. As a result
we need a bunch of string constants shared between the serialization and
deserialization process.

Currently the user defined types field is left not used, and attribute are
only referring to the user defined types as per 134. I think we should
just unroll all user types in the IR since rebuilding them will be tedious
and they will have little meaning in the backend (perhaps there is a good
reason for it that I haven't thought of?)
Fix build issues... hopefully

Copy the test folder over so gradle doesn't complain about it
LINE WIDTH!! Can we make this ~100 or something?
Renaming to const string
Merge pull request #135 from maxqchen/master

Initial deserialization code
Added variable reference expression
Renamed isSynthesizable et al
Renamed Variable::setValue to Variable::setValueExpression
Added VariableAssignmentExpression