msm: lpm_levels: remove rpm handshake in l2_gdhs mode

Remove rpm handshake in l2_gdhs mode and adjust the
latency values for l2_gdhs mode. Add a new dt entry to
inform lpm_levels driver to send sleep votes to rpm.

CRs-fixed: 604873
Change-Id: I9eeae5fada4f84ee2ca2eb9d67707dee1adf56ac
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: lpm_levels: return new idle level to cpuidle framework

Need to return the new idle level to cpuidle framework
but just returned input value argument 'index' which is
not used actually at lpm_cpu_power_select().

CRs-fixed: 601636
Change-Id: Iabd182eeb4fbdc67f4e07b40a1b593471cf8cbdf
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
PM / devfreq: Fix out of bounds access of transition table array

The previous_freq value for a device could be an invalid frequency that
results in a error value being returned from devfreq_get_freq_level().
Check for an error value before using that to index into the transition
table.

Not doing this check will result in memory corruption when previous_freq is
not a valid frequency.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Change-Id: Ia9f9f3dabf14b26c4dff54fb2bac3e77f33458c0
Signed-off-by: MassStash <MassStash@gmail.com>
msm: pm: bug in pc debug counters logic

The logic to find the location to add debug counter
for a CPU is incorrect and due to this the counter
of next CPU is corrupted. The logic is updated to
correct this.

CRs-fixed: 596773
Change-Id: I6de21bd480720d80ad9801d8a1331b6faf689b95
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
Enable KSM

Signed-off-by: MassStash <MassStash@gmail.com>
cpufreq: interactive: delete timers for GOV_START

Make sure that timers cpu_timer and cpu_slack_timer
deactivated before addition of new.

Change-Id: If31c4049606871df6f00efdc24b1d713c86a6f69
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Git-commit: b430123367e78a6557bac3cf1558bcb85193fb12
Git-repo: https://android.googlesource.com/kernel/common/
[mattw@codeaurora.org: resolved trivial context conflict]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
ion: invalidate buffers before zero'ing

Currently, we invalidate the cache for buffers being zero'd *after* we
zero them. However, this is racey since a dirty cache line from an
earlier mapping could be written out to memory between the zero'ing and
the invalidation. Fix this by invalidating the cache *before* zero'ing
the buffer.

Before this change, I was seeing corruption with:

    $ cat <<EOF | ./memory_prof -e -i -
    simple_alloc,1,ION_SYSTEM_HEAP_ID,ION_FLAG_CACHED,0x100000,1MB
    simple_basic_sanity,1
    simple_profile,1
    simple_free,1
    EOF

After this change, no corruption.

CRs-Fixed: 585524
Change-Id: I1f2603604efc9be4ebf9112b06728e0aeca60ea0
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: cpufreq: Fix msm_cpufreq_get_freq() for sync CPUs

When CPUs are in sync, only CPU0 has a non-NULL cpu_clk. clk_get_rate()
on other cpu_clk will return 0. msm_cpufreq_get_freq() is used in multiple
places in cpufreq framework to determine current hardware frequency.

Fix msm_cpufreq_get_freq() to return the right hardware frequency for
systems with synchronous CPUs.

Change-Id: I6a880764ad51fa9a257a328798b38d574750686a
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: lpm_levels: fix driver compilation issue

Assigning an unsinged long value to unsinged int is not
correct and it cause driver compilation failure. Fix by
assigning a proper value.

Change-Id: Ia8d214425c3ba07006e748bc74365da6bc22f224
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: lpm: remove redundant assignment

Removed the redundant cpu level is assignment.

Change-Id: I1aecc4f3d1eb55cd9e057c82f63b8f145401c0fc
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: msm_bus: export msm_bus_fabric_init_driver

I2c-qup driver is a client of msm_bus_fabric driver while drivers like
onsemi-ncp6335d and fan53555 are clients of i2c-qup driver. In some
targets, onsemi-ncp6335d and fan53555 drivers have to initialize and probe
early before the i2c-qup and msm_bus_fabric driver are ready. Hence export
msm_bus_fabric_init_driver to make sure msm_bus_fabric driver is ready when
its clients need to probe.

Change-Id: Ifa4f43d04f5261c49279ed9ff0e232e215066070
Signed-off-by: Ke Liu <keliu@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: msm_bus: Correct Error string while reading Clients pdata

Currently if clients miss any DT entry the error messages popping
up as "error getting pdata",which is causing ambiguity while debugging
failure cases.This patch adds correct error string for missing DT entries
and makes the error string more self-explanatory.

CRs-Fixed: 592445
Change-Id: Ic9f666d6b46722c14c77035bec3cfce09dc2b257
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
msm: pm-stats: add suspend stats reset handling

Add suspend stats reset handling to reset suspend_stats
counters and time when sending the reset command.
"echo reset > /proc/msm_pm_stats"

CRs-fixed: 610602
Change-Id: I80be31815b25ce967b50a1d0f2384250b5438420
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: peripheral-loader: Change IOMAP_SIZE from SZ_4M to SZ_1M

The ioremap call made for zeroing out trailing memory is currently
requesting for a 4M memory region. This is resulting in vmalloc
allocation failures on some platforms.
Instead, request for 1M memory locations and zero out the area
in smaller chunks to make this failure less probable.

CRs-Fixed: 613426

Change-Id: I554dc42cbb37ec893306bd1cc625230216b9b6c9
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
ARM: dts: msm: add use SW algo flags in qcrypto driver on 8974

Add optional crypto algorithm flags to indicates if to use SW crypto
algorithms instead of HW algorithms.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm: add clock management flag for qcrypto driver on 8974

Add an optional flag "clk_mgmt_sus_res" to indicate if the ce
clocks need to be disabled in suspend function and enabled in
resume function of qcrypto driver.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm: support qseecom bus scaling in msm8974

To support qseecom bus scaling, ab & ib values are changed to set four
bandwidth levels: "INACTIVE, LOW, MEDIUM and HIGH" with corresponding
bus bandwidth of {0M, 0M, 150M, 492M}; and the flag of support-bus-scaling
is also set.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm: Increase OCMEM BW request for video decode

There are framedrops observed on high bitrate clips because
OCMEM BW is not sufficient for these clips. Increase OCMEM BW
to avoid framedrops.

Change-Id: I7f3238036259e43a12899f2f7c73318328ae8eca
CRs-fixed: 571634
Signed-off-by: Vinay Kalia <vkalia@codeaurora.org>
arm/dts: 8974: Add qpnp-vadc phandle for usb3 device node

Add qpnp-vadc phandle for usb3 device node which is required
to get usb power supply's VOLTAGE_NOW property.

CRs-Fixed: 599547
Change-Id: Ia01e0620ec9a6ca28adb9e71ccac030a33a41642
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
thermal: qpnp-adc-tm: Support timer selection

Existing channels use a single timer to select the
measurement interval polling rate. Changing the interval
polling value for this timer affects the polling interval
across all the channels.

Provide an option for clients to choose from 3 of the
supported timers. Existing support has each timer linked
to a pre-configured interval polling rate. Clients can
add a optional property if it needs a specific interval
polling rate on timer2 and timer3. If the property is not
present the channel defaults to timer1 and its associated
interval polling rate.

Change-Id: Ia3c7f13081dcddb901ef446cc776f524f875fba2
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>