ARM: dts: Enable PL clocks for Parallella

Enable clocks FCLK0..FCLK3 by default for the Programmable Logic.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with e-reset and e-hw-rev tools.

Signed-off-by: Andreas Färber <afaerber@suse.de>
WIP: Epiphany reset support for E16G301

Signed-off-by: Andreas Färber <afaerber@suse.de>