Starting a new module for writing std_logic_vectors to a text file.

Copied the template for VHDL files from the tb_clockgen.vhd file.
Starting to replace the contents with appropriate information.
Got a working version of the file writer implemented into the testbenches.
Added some documentation to the tb_write_csv.vhd.  Also ran further tests on the lfsr which also happened to verify the write capabilities.  External analysis (using matlab) confirmed the random nature of the values generated by the lfsr.
Merge branch 'feature/file_write_module' into develop