v4l2-ctrls: Add unlocked version of v4l2_ctrl_modify_range

The new control range might depend on the value of the same or another
control. Drivers thus need to read control values and modify the range
atomically, which requires locking the control handler manually outside
of v4l2_ctrl_modify_range().

Remove control handler locking from v4l2_ctrl_modify_range(), rename it
to __v4l2_ctrl_modify_range() and add a static inline wrapper called
v4l2_ctrl_modify_range() that locks the control handler.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Default to the color bars test pattern

Accessing the TPG registers requires an external input clock, otherwise
an external abort exception will be triggered.

Defaulting to passthrough mode switches the timing mux to the external
clock at initialization time. If the external clock isn't provided (for
instance because the input hardware is disconnected), this results in a
kernel crash when the TPG is initialized.

Fix this by defaulting to a test pattern.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Disallow switching passthrough mode during streaming

Due to the externally supplied video timings, passthrough mode can't be
switched during video streaming, as the switch wouldn't be synchronized
to vertical sync. Allow modifying the test pattern while the stream is
active, but keep passthrough mode configuration fixed.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Make horizontal and vertical blanking configurable

In order to match the capture frame rate with the display frame rate,
video timings need to be configurable by userspace. Expose the
horizontal and vertical blanking through controls. The synchronization
pulses widths and locations don't matter for all practical purposes,
hardcode them to working values.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Ignore unconnected input ports

Follow Up Flag: Follow up
Flag Status: Flagged

When the TPG is synthesized with an input port without any input
connected, passthrough mode must not be enabled otherwise an external
abort exception will be generated. To ensure correct operation don't
allow passthrough mode when the input port doesn't have an endpoint.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] media: xilinx: Apply TPG reset on stop.

Added hack to apply TPG reset on
pipeline stop.
In current setup both vdma and TPG
are resetted. Since vdma is synced
with SOF of TPG ideally we shouldnt
need a reset.
It needs to be fixed!

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
[HACK] media: xilinx: Fix VTC timing for 1080p.

Temporary fix for programming VTC timing
generator.
TODO:
Need to explore if we can extract kernel
timing info and program it generically for
the other resolutions.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
v4l: xilinx: Add HLS core driver

Follow Up Flag: Follow up
Flag Status: Flagged

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] v4l: xilinx: Program HLS filter coefficients.

Program filter coefficients for now till
we get v4l2 user plugin implemented.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
zynq: config: add vdf defconfig

enable sobel driver
zynq: dt: add devicetrees for base trd and vdf designs