x86: Refactor x2apic_handle_read/write

Use the relative APIC registers number internally and prepare the
interface of x2apic_handle_write for returning access errors.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Move ICR access dispatching into x2apic_handle_write

More code sharing, specifically when AMD support will be added.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Filter writes to reserved APIC register bits

Set up a bitmap for all xAPIC/x2APIC register that marks reserved bits
(or complete registers). Check to-be-written values against this bitmap
before executing accesses in hypervisor context.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Filter LVT delivery modes

Do not allow cells to program anything else than Fixed mode for now. We
may have to handle NMI in the future, though, in order to support
performance counters e.g.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Update TODO

Recently added APIC topics are addressed now.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>