Allow resynthesizing project
Fix issues with makefile
Strip newlines from debug output in cosimulation mode
Detect processor halt properly with stripped newline
Fix synchronized store bug

- When a L2 response for a store came in, it was waking all threads waiting
for a store instead of the one that initiated it. This is normally somewhat
benign because the threads would just get rolled back again.  However, for
a synchronized store, it would end up completing the transaction before
the response was received from the L2 cache, which would make it appear to
have succeeded in cases where it actually didn't.
- The fix for above exposed a bug where stores wouldn't give a wakeup when
the response came in the same cycle a request was made. This is analogus to the
'near_miss' for L1 loads. Changed the logic to replace the entry with the new
request when these occur in the same cycle (this makes the code much harder to
understand, but I've tried to add clarifying comments).
Cleanup
Minor name tweak
Merge branch 'master' into fpga_bringup_debug

Conflicts:
	rtl/v2/core/l1_store_queue.v