clk: sunxi: Add support for A80 basic bus clocks

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC

This adds the gate clocks for AHB/APB busses on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i

The A80 SoC has reset controls matching bus clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Add basic clocks and reset controls

Now that we have driver support for the basic clocks, add them to the
dtsi and update existing peripherals. Also add reset controls to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Enable ARM architected timer on A80

The A80 SoC has the architected timer, but the existing firmware from
Allwinner does not set CNTFRQ at all.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>