Break width inference out into a file

I'm eventually going to have more than one simulator.  Seeing as how
this is the big block of code in the simulator I decided to break it
out into its own function.
Store the parsed cycle number

I had forgotten to actually do anything with the cycle number once I
parsed it.  This means that the simulator wasn't able to access any
cycle counts, which makes it somewhat difficult to deal with that fact
:).
Add a termination condition to the scheduler

This bails out inside the scheduler if it goes for too long without
scheduling anything.  The definition of "too long" is just the maximum
operation latency (so all the way across the chip) times the node
count.
Treat register reads and writes differently in the scheduler

Registers are really a special case: they can be read at any time, but
they have to be written in dataflow order.  I guess they _actually_
have to be written after all their readers, but that's another problem
entirely -- for now I just have a simple commit phase for registers at
the end of simulation.

I think the correct way to manage this is to simply add some
dependency from every register onto each reader of that register, but
the mechanism I currently have doesn't allow for easy reverse lookups.
This is good enough for now... :).
Add dreamer-sim-sched, the scheduled simulator

This executes a DREAMER program in exactly the order given by the
scheduler.  Right now it ensures that register reads come before
register writes by forcing that (ie, it's a two-phase loop), but that
should eventually go away.

This also removes the other scheduler tests that didn't actually do
anything but just ensured that the scheduler didn't SEGV on a few
arbitrary graphs.