Remove redundant zeroing of SREG in init code

I believe that the line zeroing out SREG can safely be omitted, saving 2 bytes. The datasheet section 7.3.1 shows that all bits in SREG get an initial value of 0...

![image](https://cloud.githubusercontent.com/assets/5520281/5591362/03a42582-9125-11e4-85e9-80359c8dd077.png)

..and the datasheet section 11.1 shows that all registers are set to their initial values upon reset...

![image](https://cloud.githubusercontent.com/assets/5520281/5591363/4587eaf6-9125-11e4-8ee5-cc19affb276e.png)