Revert "working final version, RAM not implemented"

This reverts commit b7ba71404c699e381f4690940db56da33aaf7df1.

Conflicts:
	OPCodesTesting(110714).xlsx
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ArithmeticLogicalUnit.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ControlSignal VFiles/ClockCounter.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ControlSignal VFiles/StageTracker.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/DisplayMux.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/Processor.v
	ProcessorProjectCSC317/Project 1 V Files/Formal Datapath
VFILES/RegisterFile.v
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/InstructionTestSet(11062014).mif
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.asm.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.cdf
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.done
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.eda.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.fit.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.fit.summary
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.flow.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.jdi
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.map.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.map.summary
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.pof
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.qws
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.sof
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.sta.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.sta.summary
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.v
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(0).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(0).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(1).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(1).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(10).cnf.cdb
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PROJECT/db/MasterVerilog.(10).cnf.hdb
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PROJECT/db/MasterVerilog.(11).cnf.cdb
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PROJECT/db/MasterVerilog.(11).cnf.hdb
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PROJECT/db/MasterVerilog.(12).cnf.cdb
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PROJECT/db/MasterVerilog.(12).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(13).cnf.cdb
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PROJECT/db/MasterVerilog.(13).cnf.hdb
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PROJECT/db/MasterVerilog.(14).cnf.cdb
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PROJECT/db/MasterVerilog.(14).cnf.hdb
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PROJECT/db/MasterVerilog.(15).cnf.cdb
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PROJECT/db/MasterVerilog.(15).cnf.hdb
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PROJECT/db/MasterVerilog.(16).cnf.cdb
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PROJECT/db/MasterVerilog.(16).cnf.hdb
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PROJECT/db/MasterVerilog.(17).cnf.cdb
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PROJECT/db/MasterVerilog.(17).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(18).cnf.cdb
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PROJECT/db/MasterVerilog.(18).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(19).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(19).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(2).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(2).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(20).cnf.cdb
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PROJECT/db/MasterVerilog.(20).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(21).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(21).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(22).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(22).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(23).cnf.cdb
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PROJECT/db/MasterVerilog.(23).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(3).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(3).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(4).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(4).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(5).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(5).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(6).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(6).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(7).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(7).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(8).cnf.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.(8).cnf.hdb
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PROJECT/db/MasterVerilog.(9).cnf.cdb
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PROJECT/db/MasterVerilog.(9).cnf.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.asm.qmsg
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.asm.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.asm_labs.ddb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cbx.xml
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp.bpm
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp.idb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp0.ddb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.cmp1.ddb
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PROJECT/db/MasterVerilog.db_info
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PROJECT/db/MasterVerilog.eda.qmsg
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PROJECT/db/MasterVerilog.fit.qmsg
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PROJECT/db/MasterVerilog.hier_info
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.hif
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.lpc.html
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PROJECT/db/MasterVerilog.lpc.rdb
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PROJECT/db/MasterVerilog.lpc.txt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.bpm
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.kpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.qmsg
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map_bb.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map_bb.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.pre_map.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.root_partition.map.reg_db.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.routing.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.rtlv.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.rtlv_sg.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.rtlv_sg_swap.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.sgdiff.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.sgdiff.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.sta.qmsg
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.sta.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.sta_cmp.6_slow.tdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.tmw_info
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.vpr.ammdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/logic_util_heursitic.dat
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PROJECT/db/prev_cmp_MasterVerilog_FPGA.qmsg
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.ammdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.hdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.rcfdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.cdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.dpi
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hbdb.cdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hbdb.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.kpt
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PROJECT/simulation/modelsim/MasterVerilog.vho
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PROJECT/simulation/modelsim/MasterVerilog_fast.vho
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PROJECT/simulation/modelsim/MasterVerilog_modelsim.xrf
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PROJECT/simulation/modelsim/MasterVerilog_vhd.sdo
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/simulation/modelsim/MasterVerilog_vhd_fast.sdo
Merge remote-tracking branch 'origin/master'

Conflicts:
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ArithmeticLogicalUnit.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ControlSignal VFiles/ClockCounter.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/ControlSignal VFiles/StageTracker.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/DisplayMux.v
	ProcessorProjectCSC317/Project 1 V Files/Control Unit And ALU And NON
DATAPATH VFILES/Processor.v
	ProcessorProjectCSC317/Project 1 V Files/Formal Datapath
VFILES/RegisterFile.v
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/InstructionTestSet(11062014).mif
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.asm.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.cdf
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.done
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.eda.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.fit.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.fit.summary
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.flow.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.jdi
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.map.rpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.map.summary
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PROJECT/MasterVerilog.pof
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.qws
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.sof
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/MasterVerilog.sta.rpt
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PROJECT/db/MasterVerilog.(4).cnf.hdb
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PROJECT/db/MasterVerilog.(6).cnf.cdb
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PROJECT/db/MasterVerilog.asm.rdb
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PROJECT/db/MasterVerilog.asm_labs.ddb
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PROJECT/db/MasterVerilog.cbx.xml
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PROJECT/db/MasterVerilog.cmp.bpm
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PROJECT/db/MasterVerilog.cmp.cdb
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PROJECT/db/MasterVerilog.cmp.hdb
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PROJECT/db/MasterVerilog.cmp.idb
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PROJECT/db/MasterVerilog.cmp.rdb
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PROJECT/db/MasterVerilog.cmp0.ddb
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	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.hif
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PROJECT/db/MasterVerilog.lpc.html
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PROJECT/db/MasterVerilog.lpc.rdb
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PROJECT/db/MasterVerilog.lpc.txt
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PROJECT/db/MasterVerilog.map.bpm
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PROJECT/db/MasterVerilog.map.cdb
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PROJECT/db/MasterVerilog.map.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.kpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.qmsg
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map.rdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map_bb.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.map_bb.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
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	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.root_partition.map.reg_db.cdb
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PROJECT/db/MasterVerilog.routing.rdb
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PROJECT/db/MasterVerilog.rtlv.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.rtlv_sg.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/db/MasterVerilog.rtlv_sg_swap.cdb
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PROJECT/db/MasterVerilog.sgdiff.cdb
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PROJECT/db/MasterVerilog.sgdiff.hdb
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PROJECT/db/MasterVerilog.sta.qmsg
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PROJECT/db/MasterVerilog.sta.rdb
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PROJECT/db/MasterVerilog.sta_cmp.6_slow.tdb
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PROJECT/db/MasterVerilog.vpr.ammdb
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PROJECT/db/logic_util_heursitic.dat
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PROJECT/db/prev_cmp_MasterVerilog_FPGA.qmsg
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.ammdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.cmp.rcfdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.dpi
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hbdb.cdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hbdb.hdb
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PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.hdb
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/incremental_db/compiled_partitions/MasterVerilog.root_partition.map.kpt
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/simulation/modelsim/MasterVerilog.vho
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PROJECT/simulation/modelsim/MasterVerilog_fast.vho
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/simulation/modelsim/MasterVerilog_modelsim.xrf
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/simulation/modelsim/MasterVerilog_vhd.sdo
	ProcessorProjectCSC317/Project 1 V Files/MasterVerilog And MIF
PROJECT/simulation/modelsim/MasterVerilog_vhd_fast.sdo