MFC 264990, 264994, 265020, 265025:

  Call cpu_icache_sync_range() rather than sync_all since we know the range
  and flushing the entire icache is needlessly expensive.

  Provide a proper armv7 implementation of icache_sync_all rather than
  using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
  operation to other cores.  In elf_cpu_load_file() use icache_sync_all()
  and explain why it's needed (and why other sync operations aren't).

  Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.

  Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
  flush.  (Either it was missing here, or it isn't needed in the minidump
  case.  Adding it here seems like the safer path to consistancy.)
MFC 265023, 265024, 265036:

  There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
  map them both to the same interrupt number like other arches do.

  Flush and invalidate caches on each CPU as part of handling IPI_STOP.

  Don't use multiprocessing-extensions instruction on processors that don't
  support SMP.
MFC 265035: Move duplicated code to print l2 config into the common code.
MFC 265038:

  Move common device tree informations to separate dtsi files for A10 and
  A20 SoC. Change cubieboard1 and cubieboard2 dts files accordingly.
MFC 265059: Set the new floating point exception mask correctly.