Changed verilog handling, added core_info/bof gen

Removed verilog instance classed -- now everything is a module,
you can choose to instantiate modules within other modules to
get the old behaviour.
Changed yellow blocks to be compatible with this.

added wishbone device class to hold various memory details. toolflow
now generates core_info.tab
Added ngc files to needed sources for ISE compiles
Changed epb clock to 67 MHz.

and removed copy-paste error on first line
Added mkbof_64

No, I won't be adding mkbof.exe
Changed verilog handling, added core_info/bof gen

Removed verilog instance classed -- now everything is a module,
you can choose to instantiate modules within other modules to
get the old behaviour.
(this should have been commited with the other verilog stuff)
Changed all the [0:31] indices to [31:0]