Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs.

We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op.  Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.

In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer.  In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.

Submitted by:	Michal Meloun <meloun@miracle.cz>
No functional changes.  Remove a couple outdated or inane comments and
add new comment blocks describing why the cache maintenance sequences are
done in the order they are for each case.