intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03

GP0e does not fit into the naming scheme of the field units surrounding
this field unit definition. Also the keys for e and 3 are close to each
other supporting the theory that this is indeed a typo.

Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5483
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Update vendorcode/intel/makefile for coming FSPs

Other FSPs have more than just the initial fsphob.c source file.
Add any .c files in the srx directory to the ramstage build.

Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add the ivybridge i89xx FSP include & srx directories

These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Firmware Support Package for Intel® Xeon® E3-1125C v2,
E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™
i3-3115C Processors for Communications Infrastructure with
Intel® Communications Chipset 89xx Series Platform Controller Hub
(formerly Crystal Forest Refresh: Ivy Bridge Gladden and Cave Creek

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: Ib76e89b2d2f6407cf55a5a664da989c7a7e0eb23
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5455
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add the Bay Trail FSP include & srx directories

These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Atom™ processor E3800 product family (formerly Bay Trail)

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5456
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add the Rangeley FSP include & srx directories

These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Firmware Support Package for Intel® Atom™ Processor C2000
Product Family (Formerly Rangeley)

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: I9ed94cb92909c3681cc88bf10b85a9ba25e8fc55
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5457
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
agesa: Always include family* Kconfig

Otherwise we generate a recursive dependency because
CPU_AMD_AGESA depends on the per-family configurations
while those only exist if CPU_AMD_AGESA is selected.

Change-Id: Ic08d517ff4ca8bb76afc1574b55c54b28ec3f1b0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5490
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ec/compal/ene932/acpi: Let mainboard define the ACPI lid object

The GP15 ACPI object was used to get the state of the lid. However
GP15 is specific to certain Intel chipsets, and will not always be in
the ACPI namespace. Instead of hardcoding this object, let the
mainboard define it.

Also, document the ACPI interface for the EC.

Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5444
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
hp/pavilion_m6_1035dx: Add ACPI support for reading battery level

Hook in the EC ASL code. This provides just enough information for the
OS to be able to read the battery information.

EC notifications (_Qxx) do not yet work, and it is unclear if the
issue is in the ACPI code, or if the EC is not set up properly. Thus,
the OS must boot with the battery inserted in order to be able to read
its status.

The _L03 ACPI method is also removed, as the EC SCI uses this event.

Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI

Only the WLAN control pin and the lid switch input are declared, as
those are the only pins whose function is known and tested.

Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5463
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
hp/pavilion_m6_1035dx: Add ACPI support for lid switch

This is sufficient to at least allow linux to recognize the lid switch
and read its state correctly.

Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5464
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
hp/pavilion_m6_1035dx: Add basic EC initialization

The EC is now set to ACPI mode, and properly generates SCIs on
external events. This fixes the issue where battery notifications were
not working.
The keyboard matrix type is also explicitly set up.

Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pin

Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Put EC in APM mode before ACPI mode

The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. The
workaround is to put it in APM mode before switching it to ACPI mode.

Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[RFC] ec/compal/ene932: Update to use coreboot EC API

This is based on the EC-mainboard interaction draft specification [1]

Enjoy the clusterURL in clustercommit clustermessage.

[1] http://www.coreboot.org/ACPI/Board-EC_interaction#The_mainboard_namespace_method

Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey

Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method

Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
usbdebug: Reduce bus reset delays

According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.

Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
usbdebug: Add optional quirk for old DIY debug part

Not sure what this is about. Required for FX2.

Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
vendorcode/amd/agesa/fam15tn: Build as a static library

Up until now, we were building AGESA by specifying each AGESA source
file and adding it to the list of romstage and ramstage source files.
As a result, we were compiling each AGESA source twice, despite the
fact that it does not depend on the stage we're in.

Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

We still keep the practice of specifying every single AGESA directory
as an include dir and adding the AGESA CFLAGS to our global CFLAGS;
this is needed due to the way AGESA builds.

Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/amd/agesa/hudson: Clean up AGESA #includes

NOTFORMERGE: EDIT commit message to include proper hash

Just like in commit
<HASH HERE> vendorcode/amd/agesa/fam15tn: Clean #includes in public headers

Include AGESA headers specifying the path relative to AGESA_ROOT. The
path is specified relative to AGESA_ROOT as opposed to src/ since this
code may include headers from different AGESA families, depending on
the board.

Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>