Consolidate DMA entries and do a better job of catching 1MB rollovers.
Add a 60s timeout if the DMA working.
QSys updates...

* Add reset and clock bridge so I can reset both sides of the DC FIFO and write master.
* Disable response from SGDMA dispatcher so it doesn't fill up and stop DMA's
* Change to 16bit wide data input.
Proper latched pulse counting with Flancters

Also add 200MHz system clock.
Add library for easy calling from python.
Some python scraps for testing.
Forgot to add this for shared library.