generate the outPacket with a Cat-statement and test the ram-tile with a read request
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Test writing to an address other than 0. There is a bug with the ram when it is made sequential with a register, so that the value is made ready but with the incorrect result. I've removed the register temporarily in order to get the value the same cycle a read reqiuest is issued. It might be the EnqIO that creates the problem, by setting the vali-bit high before the value is ready
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Test sequential read and write of ram-tile. The test issues 8 write-requests, then 8 read-requests and then verifies 8 read-responses from the ram-tile