decode: do not generate illegal insn exception on l.msync

l.msync is a class II instruction, which means that it is
optional to implement.
However, this doesn't mean that the instruction should
generate an illegal instruction exception when it's not
implemented, instead the arch spec states that it should
instead be implemented as a no-op on implementations
that has strongly ordered memory accesses.

To be consistent, parameters are added for all three
sync instructions, l.msync, l.psync and l.csync.
None of them have actual implementations, and l.psync and
l.csync will generate illegal insn exceptions when their
parameters are defined as "NONE".
propagate OPTION_PIC_NMI_WIDTH all the way up to top level

This was accidently omitted when the OPTION_PIC_NMI_WIDTH
parameter was introduced.
cfgrs: whitespace cleanup and switch to verilog2001 module declaration
add support for shadow register files

This adds an additional parameter, that configure the number
of shadow register files are present.
This functionality is related to the fast contexts, but
that feature is not yet implemented.

Software can however make use of the shadowed rf without
the fast context functionality, by reading and writing the
shadowed register file by spr accesses.
Reading the RF over spr was already supported,
but this also adds write support.