made nameSpace global
Uniquify names on a per-module basis

Name mangling resulted in occasional collisions, e.g. foo.bar would become
foo_bar, which could conflict with a node truly named foo_bar.
Merge branch 'master' of https://github.com/ucb-bar/chisel into ir
fixed Verilog clk domain outputs
defined nameIt for CompositeData
before merge: directly access updates instead of using when statements
after merge
fixed counter bugs