ARM: l2c: AM43x: add L2 cache support

Add support for L2 cache controller (PL310) on AM437x SoC.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: prima2: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: prima2: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  Along with this change, we can delete l2x0.c
from prima2.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: realview: improve commentry about the L2 cache requirements

Add better commentry about the L2 cache requirements on these platforms.
Unfortunately, the auxiliary control register is not pre-set to indicate
the correct cache parameters, so we have to manually program these.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: rockchip: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: shmobile: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: socfpga: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: spear13xx: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: sti: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  We can remove the .init_machine as it becomes
the same as the generic version.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: tegra: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: tegra: convert to common l2c310 early resume functionality

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: tegra: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: ux500: implement dummy write_sec method

ux500 can't write to any of the secure registers on the L2C controllers,
so provide a dummy handler which ignores all writes.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: ux500: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: ux500: don't try to change the L2 cache auxiliary control register

ux500 can't change the auxiliary control register, so there's no point
passing values to try and modify it to the l2x0 init functions.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: vexpress ca9x4: move L2 cache initialisation earlier

It is beneficial to have the L2 cache up and running earlier in the
system boot.  Not only will this allow for simpler code when we come to
enable some features, but it also means that we get a more accurate
bogomips value for the udelay() loop.  Calibrating the loop with the
L2 cache off, and then running with the L2 cache on is not the best
idea.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: vexpress: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: zynq: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: zynq: convert to generic l2c OF initialisation

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this

L2X0_AUX_CTRL_MASK is not useful for PL310s.  It would be better if
people thought about their value for this rather than cargo-cult
programming.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>