hdl/testbench/*/wb_acq_core_test/*: shorten 200MHz reset delay

The 7 series async FIFO will misbehave if the read clk is
asserted at the same cycle as the reset is deasserted, causing
the FIFO to become full and the output to become undefined (X's).
The difference in the reset delays give sufficient ammount of time
for the FIFO to correctly reset itself.