WORKING Submission Project # 1 - Phase # 2...

Submission Was (CSC317-Project(11082014)bFINALwoRAM)
Edited Modules In ((CSC317-Phase2Project(11092014)a) )NOT WORKING
-MemoryInterface
-StageTracker
-SelectControler

3:38 PM 11/9/2014

Phase#2 Notes:
-LBI and LDRI Have Been Implemented But Not Tested
-All other instructions have been validated using

Project Arithmetic Validation:
1.)  Open "*\CSC317-Project1-Phase#2\ProcessorProjectCSC317\Project 1 V
Files\MasterVerilog And MIF PROJECT\MasterVerilog_FPGA.qpf"

2.a) Using "InstructionTestSet(11062014).mif"
2.b) View the outputs of the processor at each stage, for each
instruction:
USING the case statement in display mux, controlled by switches[4:0],
and peek into the register file using the additonal switches[17:13]
("*\CSC317-Project1-Phase#2\ProcessorProjectCSC317\Project 1 V
Files\Control Unit And ALU And NON DATAPATH VFILES/DisplayMux.v")

2.c) Compare the outputs with the expected outputs detailed in
"*\CSC317-Project1-Phase#2\Phase2Validation.xlsx"