sim: use (mandatory) ncycles when starting a simulation with no active functions
genlib/fifo: add SyncFIFORelaxed

In some instances XST fails to map SyncFIFO to BRAM because of the
asynchronous read. This adds a FWFT FIFO that always registers dout and
should be mappable to BRAM in all cases. It also adds a bypass around
the entire thing to achieve the same behavior and latency as SyncFIFO.