[NVPTX] Rename registers %fl -> %fd and %rl -> %rd

This matches the internal behavior of NVIDIA tools like libnvvm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213168 91177308-0d34-0410-b5e6-96231b3b80d8
Added documentation for SizeMultiplier in the ARM subtarget hook for register coalescing. Also fixed some 80 col violations.

No functional code changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213169 91177308-0d34-0410-b5e6-96231b3b80d8
Track clang r213171

The clang rewriter is now a core facility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213173 91177308-0d34-0410-b5e6-96231b3b80d8