ntb: Add alignment check to meet hardware requirement

The NTB translate register must have the value to be BAR size aligned.
This alignment check make sure that the DMA memory allocated has the
proper alignment. Another requirement for NTB to function properly with
memory window BAR size greater or equal to 4M is to use the CMA feature
in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and
CONFIG_CMA_SIZE_MBYTES set.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
NTB: debugfs device entry

Create a debugfs entry for the NTB device to log the basic device info,
as well as display the error count on a number of registers.

Signed-off-by: Jon Mason <jon.mason@intel.com>
ntb: move platform detection to separate function

Move the platform detection function to separate functions to allow
easier maintenence.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
ntb: conslidate reading of PPD to move platform detection earlier

To simplify some of the platform detection code. Move the platform detection
to a function to be called earlier.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
ntb: use errata flag set via DID to implement workaround

Instead of using a module parameter, we should detect the errata via
PCI DID and then set an appropriate flag. This will be used for additional
errata later on.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
ntb: Adding split BAR support for Haswell platforms

On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
ntb: workaround for high traffic hardware hang

A hardware errata causes the NTB to hang when heavy bi-directional traffic
in addition to the usage of BAR0/1 (where the registers reside, including
the doorbell registers to trigger interrupts).

This workaround is only available on Haswell platform.
The workaround is to enable split BAR in the BIOS to allow the 64bit BAR4 to
be split into two 32bit BAR4 and BAR5. The BAR4 shall be pointed to LAPIC
region of the remote host. We will bypass the doorbell mechanism and directly
trigger the MSIX interrupts. The offsets and vectors are exchanged during
transport scratch pad negotiation. The scratch pads are now overloaded
in order to allow the exchange of the information. This gets around using
the doorbell and prevents the lockup with additional pcode changes in BIOS.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>