x86jit: Improve cvt.w.s when fd is loaded or fs.

We have no need to store it.
x86jit: Optimize neg.s and abs.s a tiny bit.

Same reg is probably a common case, improves micro benchmark.
x86jit: Very small optimization to c.nge.s.
x86jit: Small optimization for add.s f1, f2, f2.

Doubles the speed of that particular case.  Biggest difference is not
loading fd for no reason.
x86jit: Implement round.w.s and friends.

They are not terribly fast, though, updating MXCSR.
x86jit: Avoid speculative loads in mtc1/mfc1.
x86jit: Optimize loads of 0 into fp regs.
x86jit: Micro optimize slt* a bit.

This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.
Clarify a comment.
Merge pull request #7074 from unknownbrackets/jit-minor

x86jit: More fpu optimizations
unittest: Have the JIT harness print disassembly, to make it easy to inspect results.
Revert "x86jit: Micro optimize slt* a bit."

This reverts commit ee66596b8d441275dd9741d15ed365fec75774f2.

Broke a lot of games, probably some small bug.

Conflicts:
	Core/MIPS/x86/CompALU.cpp
Collapse sequences of "int3" (padding after block linking) in x86 disassembly.
Properly prevent loading ISO to RAM in 32-bit mode (could have been enabled in 64-bit mode where the UI exists)
x86 JIT: EBX was free in 32-bit mode, let's use it in the regcache.
Rebase RadarNyan work on Generate version while build on Wiondows
Merge branch 'windows-exe-version' of https://github.com/RadarNyan/ppsspp into verbuild

Conflicts:
	Windows/version.rc